VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC838

3.2Gb/s

36x37 Crosspoint Switch

G52351-0, Rev 3.0

Page 7

02/12/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Figure 3: Serial Mode (leave ALE_SCN pin LOW during programming)

Figure 4: Serial Read-Back

NOTE: The word pattern during serial read back will be four valid words followed by four ‘DON’T CARE’ words.

SDOUT

LOAD

CONFIG

T

hSDIN

T

PWCFG

INCHAN1_SCLK

INCHAN0_SDIN

Y5

Y4

Y3

Y2

low

Y1

Y0

A5

A4

A3

A2

low

A1

A0

Y5

Y4

Y3

Y2

T

sSDIN

SERIAL

T

sSERIAL

T

dSDOUT

T

hLOAD

T

sLOAD

T

perSCLK

CS

T

sCS

T

hCS

Y(n) = Output Address Bit (n); A(n) = Input Address Bit (n)

SDOUT

ALE_SCN

T

sSCAN

INCHAN1_SCLK

36

b5

T

hSCAN

SERIAL

T

sSERIAL

T

dSDOUT

36

b4

36

b3

36

b2

36

b1

36

b0

35

b5

35

b4

35

b3

35

b2

35

b1

35

b0

34

b5

MSB of Program memory for

Activity Monitor Channel

Read-back shift register (483 bits long) is loaded here

on rising edge of INCHAN1_SCLK with SERIAL HIGH

and ALE_SCN LOW

T

perSCLK

36

low

35

low

output channel