MB91307 datasheet(18/96 Pages) FUJITSU

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MB91307 Series

• Terminal and timing control register (TCR) (0x00000683)

The terminal and timing control register (TCR) is a write-only register. Therefore, do not access TCR with a bit

manipulation instruction.

If you intend to disable sharing of the bus by writing “0” to Bit 7 (BREN bit) of TCR when the bit is “1”, be sure

to follow the procedure below. If the procedure is not followed, the device may hang up.

1. Write “0” to Bit 2 (BRQE bit) of the port 8 function register (PFR8).

2. Write “0” to Bit 7 (BREN bit) of TCR.

• RD/WR → CS hold extension cycle

Assume that use of the RD/WR

→ CS hold extension cycle is specified (Bit 0 of AWR is 1) for an

area for which the normal memory/IO access type is set (the TYPE3 to TYPE0 bits of ACR are

0xxx). Even in this case, the hold extension cycle might not be inserted when the operation and

settings are specified in a specific combination.

The hold extension cycle will not be inserted when the following conditions are met:

• Use of the RD/WR

→ CS hold extension cycle is specified.

(Bit 0 [W00 bit] of AWR is 1.)

• A normal memory/IO access type is set for the area.

(Bits 3 to 0 [TYPE3 to TYPE0 bits] of ACR are 0xxx.)

Note: The MB91307 series allows only this type to be set.

• Disuse of the address

→ CS delay cycle is specified.

(Bit 2 [W02 bit] of AWR is 0.)

• A setting (recovery enabled) other than 0 cycle is made for the write recovery cycle.

(Bits 5 and 4 [W05 and W04 bits] of AWR are other than 00.)

(Example: First word writing to an external bus 16-bit area)

• If an access is made to write data larger than the bus width to the relevant area under the above conditions,

the RD/WR-CS hold extension cycle is not inserted in any cycle other than the last cycle to write divisions of

the data. Therefore, the hold time becomes insufficient.

Note : This problem does not occur in the read cycle.

To use this function, make either of the following settings:

• Specify the use of the address

→ CS delay cycle.

(Set 1 for Bit 2 [W02 bit] of AWR.)

• Specify 0 cycle for the write recovery cycle.

(Set 00 for Bits 5 and 4 [W05 and W04 bits] of AWR.)

• Signed DIVIDE statement (DIVOS)

When the instruction immediately before the instruction of DIVOS is an instruction by which the memory access

is done, a correct calculation result might not be obtained.

This is generated under the following conditions.

• When the instruction performs memory accesses just before a DIVOS instruction.

Note : Instructions that performs relevant memory accesses (a total of 58 instructions)

ST Ri, @- R15

ST Rs, @- R15

ST PS, @- R15

STB Ri, @Rj

STB Ri, @ (R13, Rj)

DMOVB R13, @dir8

STB Ri, @ (R14, disp8)

LDUB @Rj, Ri

LD @ (R13, Rj), Ri

LDUH @ (R13, Rj), Ri

LDUB @ (R13, Rj), Ri

DMOV @dir10, R13

DMOVH @dir9, R13

DMOVB @dir8, R13

LD @ (R14, disp10), Ri

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