MB91307 datasheet(2/96 Pages) FUJITSU

2 / 96 page

MB91307 Series

• Easier assembler notation: register interlock function

• Built-in multiplier/instruction level support

Signed 32-bit multiplication: 5 cycles

Signed 16-bit multiplication: 3 cycles

• Interrupt (PC, PS removal): 6 cycles, 16 priority levels

• Harvard architecture for simultaneous execution of program access and data access

• CPU hold 4-word queue allows advanced instruction fetch function

• 4G bytes expanded memory space enables linear access

• Instruction compatible with FR30/40 family

Bus Interface

• Operating frequency: Max 33 MHz

• 8- or 16-bit data output

• Built-in pre-fetch buffer

• Unused data/address pins can be used as general-0purpose input/output ports

• Fully independent 8-area chip select outputs, can be set in minimum 64K bytes units

• Interface support for many memory types

SRAM, ROM/Flash

Page mode flash ROM, page mode ROM interface

Burst mode flash ROM (select burst length 1, 2, 4, 8)

• Basic bus cycle: 2 cycles

• Programmable by area with automatic wait cycle generation to enable wait insert

• RDY input for external wait cycles

• DMA supports fly-by transfer with independent I/O wait control

Built-in RAM

• 128K bytes (MB91307R), 64K bytes (MB91306R)

• Accepts writing of data and instruction codes, enabling use as instruction RAM

Instruction cache

• 1K bytes capacity

• 2-way set associative

• 4-words (16 bytes) per set

• Lock function enables permanent program storage

• Areas not used for instruction cache can be used for RAM

DMAC (DMA controller)

• 5-channel (3-channel external-to-external)

• 3 transfer sources (external pin, internal peripheral, software)

• Addressing mode with 32-bit full address indication (increment, decrement, fixed)

• Transfer mode (demand transfer / burst transfer / step transfer / block transfer)

• Fly-by transfer support (3 channels between external I/O and external memory)

• Transfer data size selection 8/16/32-bit

Bit search module (using REALOS)

• Searches words from MSB for first bit position of a 1/0 change

Reload timer (includes 1 channel for REALOS)

• 16-bit timer: 3 channels

• Internal clock multiplier choice of x2, x8, x32

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