MB91307 datasheet(21/96 Pages) FUJITSU

21 / 96 page

MB91307 Series

❍Unique to the evaluation chip MB91V307R

• Simultaneous occurrences of a software break and a user interrupt/NMI

When a software break and a user interrupt /NMI take place at the same time, the emulator debugger can cause

the following phenomena:

• The debugger stops pointing to a location other than the programmed breakpoints.

• The halted program is not re-executed correctly.

If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has

been used, avoid setting any break at the relevant location.

• Single-stepping the RETI instruction

If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly

after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being

executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant

interrupt routine becomes unnecessary, perform debugging with that interrupt disabled.

• Break function

• If the address of a current system stack pointer or an area that includes a stack pointer is specified as an

object address of a hardware break (including an event break), a break occurs after one instruction is executed.

The break occurs although the relevant user program does not include an actual data access instruction. To

avoid this problem, do not set the (word) access to an area that includes the address of a system stack pointer

as a target of a hardware break (including an event break).

• If an instruction that causes a wait is executed between an instruction to read a branch destination address

from memory and a branch instruction, an instruction alignment error occurs at a point where an instruction

alignment error cannot occur originally. Then, an ICE break (CPU error break) occurs, and execution of

instructions stops. Furthermore, even if an instruction break is set for the branch destination address at the

point where the above error occurs, a break might not occur.

Example: LD

@R1,R0 ; read F-bus RAM

@R2,R3 ; read F-bus RAM

CALL

@R0

; An incorrect alignment error may occur or a break might not occur.

To avoid the incorrect alignment error as described above, turn off the alignment error function in debugger

function setup.

To perform the instruction break correctly, do not specify use of a hardware break, but specify use of a software

break in debugger function setup.

• Trace mode

If the trace mode for debugging is set to full trace mode, which uses internal FIFO memory as the output buffer,

the current may increase or DMA access to the D-bus may be lost.

This is occurred if:

• A DMA transfer to the D-bus or standby mode occurs in full trace mode.

Use internal trace mode to avoid this notes.

MB91307 Datasheet(PDF) 21 Page - fujitsu semiconductor