AD7298 datasheet(21/25 Pages) AD

21 / 25 page

AD7298

Rev. B | Page 20 of 24

Full Power-Down Mode

In this mode, all internal circuitry on the AD7298 is powered

down and no information is retained in the control register or any

other internal register. If the averaging feature for the tempera-

ture sensor is enabled in the control register (TSENSEAVG), the

averaging is reset once the device enters power-down mode.

The AD7298 is placed into full power-down mode by bringing

the logic level on the PD/RST pin low for greater than 100 ns.

When placing the AD7298 in full power-down mode, the ADC

inputs must return to 0 V. The PD/RST pin is asynchronous to

the clock, thus it can be triggered at any time. The part can be

powered up for normal operation by bringing the PD/RST pin

logic level back to a high logic state.

The full power-down feature can be used to reduce the average

power consumed by the AD7298 when operating at lower

throughput rates. The user should ensure that tPOWER_UP has

elapsed prior to programming the control register and initiating

a valid conversion.

POWERING UP THE AD7298

The AD7298 contains a power-on reset circuit, which sets

the control register to its default setting of all zeros, thus the

internal reference is enabled and the device is configured for the

normal mode of operation. On power-up, the internal reference

is by default enabled, which takes up 6 ms (maximum) to

power-up.

If an external reference is being used, the user does not need to

wait for the internal reference to power-up fully. The AD7298

digital interface is fully functional after 500 μs from initial

power-up. Therefore, the user can write to the control register

after 500 μs to switch to external reference mode. The AD7298

is then immediately ready to convert once the external reference

is available on the VREF pin.

When supplies are first applied to the AD7298, the user must

wait the specified 500 μs before programming the control

RESET

The AD7298 includes a reset feature that can be used to reset

the device and the contents of all internal registers, including

the control register, to their default state.

To activate the reset operation, the PD/RST pin should be

brought low for no longer than 100 ns. It is asynchronous with

the clock, thus it can be triggered at any time. If the PD/RST pin

is held low for greater than 100 ns, the part enters full power-

down mode. It is imperative that the PD/RST pin be held at a

stable logic level at all times to ensure normal operation.

AD7298 Datasheet(PDF) 21 Page - Analog Devices

AD7298 Datasheet(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Datasheet Download

Link URL