843051AG

www.icst.com/products/hiperclocks.html

REV. A DECEMBER 14, 2004

9

Integrated

Circuit

Systems, Inc.

ICS843051

XTAL2

R1

1K

+

-

Zo = 50 Ohm

R3

133

R4

82.5

Q

X1

19.44MHz

VCC

C2

33pF

C5

0.1u

C3

10uF

C4

0.1u

R6

82.5

R2

10

VCC

C1

27pF

VCC

18pF

XTAL1

U1

ICS843051

1

2

3

4

8

7

6

5

VCCA

VEE

XTAL2

XTAL1

VCC

Q0

nQ0

FREQ_SEL

VCC

nQ

R5

133

Zo = 50 Ohm

VCCA

Figure 3A shows a schematic example of the ICS843051. An

example of LVEPCL termination is shown in this schematic.

Additional LVPECL termination approaches are shown in the

LVPECL Termination Application Note. In this example, an 18 pF

parallel resonant crystal is used. The C1 = 27pF and C2 = 33pF

are recommended for frequency accuracy. The C1 and C2 val-

ues may be slightly adjusted for optimizing frequency accuracy.

XTAL_IN

XTAL_OUT

Figure 3B shows an example of ICS843051 P.C. board layout.

The crystal X1 footprint shown in this example allows installa-

tion of either surface mount HC49S or through-hole HC49 pack-

age.The footprints of other components in this example are listed

in the

Table 6. There should be at least one decoupling capacitor

per power pin. The decoupling capacitors should be located as

close as possible to the power pins. The layout assumes that

the board has clean analog power ground plane.

e

c

n

e

r

e

f

e

Re

z

i

S

2

C

,

1

C2

0

4

0

3

C5

0

8

0

5

C

,

4

C3

0

6

0

2

R3

0

6

0

t

n

e

n

o

p

m

o

c

s

t

s

il

,

6

e

l

b

a

T

:

E

T

O

N

.

e

l

p

m

a

x

e

t

u

o

y

a

l

s

i

h

t

n

i

n

w

o

h

s

s

e

z

i

s