Data bit : R/G/B, CONT

Control bit : V,HSYNC

Data bit : CTL*

H

L

DE

THCV234

THCV233

R/G/B,

CONT,

CTL

V,

HSYNC

DE=H R/G/B,CONT

DE=L, CTL* except the 1st and the last pixel

other R/G/B,CONT=Low Fixed

DE=H, V,HSYNC=Fixed

DE=L, V,HSYNC

DE

*CTL are particular assigned bit among R/G/B, CONT that can carry arbitrary data during DE=Low period.

TLCLK +/-

6

543210

D

E

V

H

3210

TLn +/-

n=A,B,D,E

TLC +/-

6

543210

D

E

VH

3

2

1

0

6

543210

D

E

VH

3

2

1

0

6

543210

D

E

VH

3

2

1

0

6

543210

D

E

VH

3

2

1

0

6

543210

D

E

VH

3

2

1

0

DE=High

Active period

DE=Low

Blanking period

Data : Low fixed

H, V : Keep the last data of blanking period

THCV233

input

THCV234

output

DE input via LVDS

Data : Particular assigned bit CTL is transmitted except the

first and the last pixel of Blanking period. / Others are Low fixed.

RLCLK +/-

6

543210

RLn +/-

n=A,B,D,E

RLC +/-

6

543210

6

543210

6

543210

6

543210

6

543210

6

543210

0

321

0

21

H

V

H

V

VH

Indefinite region

Indefinite region

DEOUT

(CMOS)

±3/7tTCIP

543

543

43

21

21

21

21

543

543

543

210

1

21

21

21

21

±3/7tTCIP

tRALN

tRALN

Indefinite region

Typ;5tTCIP/7

Typ;5tTCIP/7