AS0142AT datasheet(35/45 Pages) ONSEMI

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AS0142AT

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SINGLE WRITE TO RANDOM LOCATION

Figure 32 shows the typical WRITE cycle from the host

to the AS0142AT. The first 2 bytes indicate a 16−bit address

of the internal registers with most−significant byte first. The

following 2 bytes indicate the 16−bit data.

Reg Adress, N

Reg Addr ess, M

M+1

Slav

e Address

Reg Address[15:8]

Reg Address[7:0]

Write Data

Figure 32. Single WRITE to Random Location

SEQUENTIAL WRITE, START AT RANDOM LOCATION

This sequence (Figure 33) starts in the same way as the

single WRITE to random location (Figure 32). Instead of

generating a no−acknowledge bit after the first byte of data

has been transferred

, the master generates an acknowledge

bit and continues to perform byte writes until “L” bytes have

been written. The WRITE is terminated by the master

generating a stop condition.

Write Da

W rr iitete Da Da tata

Write Da ta

(15:8)

Write Da ta

(7:0)

Write Da ta

(15:8)

Write Da ta

(7:0)

Previous Re

g Addre

ss, N

Reg Address, M

M+1

Slave Address

Reg Address[15:8]

Reg Address[7:0]

Write Data

M+1

M+2

M+3

M+L−2

M+L−1

M+L

Write Data

(15:8)

Write Da ta

(7:0)

Write Da ta

(15:8)

Write Da ta

(7:0)

Figure 33. Sequential WRITE, Start at Random Location

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