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AD7693

Data Sheet

SUPPLYING THE ADC FROM THE REFERENCE

For simplified applications, the AD7693, with its low operating

current, can be supplied directly using the reference circuit

shown in Figure 33. The reference line can be driven by

•

The system power supply directly

•

A reference voltage with enough current output capability,

such as the ADR43x

•

A reference buffer, such as the AD8031, which can also

filter the system power supply, as shown in Figure 33.

AD8031

AD7693

VIO

REF

VDD

10µF

1µF

Ω

10k

Ω

1µF

1OPTIONAL REFERENCE BUFFER AND FILTER.

Figure 33. Example of an Application Circuit

DIGITAL INTERFACE

Generally, a user is interested in either minimizing the wiring

complexity of a multichannel ADC system or communicating

with the parts via a specific interface standard. Although the

ADC has only four digital pins (CNV, SCK, SDI, and SDO), it

offers a significantly flexible serial interface, including

compatibility with SPI, QSPI, digital hosts, and DSPs (such as

Blackfin® ADSP-BF53x or ADSP-219x). By configuring the

ADC into one of six modes, virtually any serial interface

scenario can be accommodated.

For wiring efficiency, the best way to configure a multichannel,

simultaneous-sampling system is to use the 3-wire chain mode.

This system is easily created by cascading multiple (M) ADCs

into a shift register structure. The CNV and CLK pins are

common to all ADCs, and the SDO of one part feeds the SDI of

the next part in the chain. The 3-wire interface is simply the

CNV, SCK, and SDO of the last ADC in the chain. For a system

containing M- and N-bit converters, the user needs to provide

M × N SCK transitions to read back all of the data. This 3-wire

interface is also ideally suited for isolated applications.

Additional flexibility is provided by optionally configuring the

ADCs to provide a busy indication. Without a busy indication,

the user must externally timeout the maximum ADC conversion

time before commencing readback. This configuration is described

in the Chain Mode Without Busy Indicator section. With the

busy indication enabled, external timer circuits are not required

because the SDO at the end of the chain provides a low-to-high

transition (that is, a start bit) when all of the chain members have

completed their conversions and are ready to transmit data.

However, one additional SCK is required to flush the SDO busy

indication prior to reading back the data. This configuration is

described in the Chain Mode with Busy Indicator section.

The primary limitations of 3-wire chain mode are that all ADCs

are simultaneously sampled and the user cannot randomly select

an individual ADC for readback. This can be overcome only by

increasing the number of wires (for example, one chip select

wire per ADC). To operate with this increased functionality, the

part must be used in CS Mode. CS mode is separated into two

categories (3-wire and 4-wire) whereby flexibility is traded off for

wiring complexity. In CS 4-wire mode, the user has independent

control over the sampling operation (via CNV) and the chip

select operation (via SDI) for each ADC. In CS 3-wire mode,

SDI is unused (tied high) and CNV is used to both sample the

input and chip select the part when needed. As with chain

mode, the parts can optionally be configured to provide a busy

indication, but at the expense of one additional SCK when

reading back the data. So in total there are four CS modes:

3-wire and 4-wire modes, each with busy and without busy.

There is no elaborate writing of configuration words into the

part via the SDI pin. The mode in which the part operates is

defined by ensuring a specific relationship between the CNV,

SDI, and SCK inputs at key times. To select CS mode, ensure

that SDI is high at the rising edge of CNV; otherwise, chain

mode will be selected. Once in CS mode, selecting the part for

readback before the conversion is complete (by bringing either

SDI or CNV low) instructs the part to provide a busy indicator,

a high-to-low impedance transition on SDO, to tell the user

when the conversion has finished. If the part is selected after the

conversion has finished, SDO outputs the MSB when it is

selected. In chain mode, the busy indicator, a low-to-high

transition on SDO, is selected based on the state of SCK at the

rising edge of CNV. If SCK is high, the busy indicator is

enabled; otherwise, the busy indicator is not enabled.

The following sections provide specifics for each of the different

serial interface modes. Note that in the following sections, the

timing diagrams indicate digital activity (SCK, CNV) during

conversion. However, due to the possibility of performance

degradation, digital activity should only occur during the first

quarter of the conversion phase because the AD7693 provides

error correction circuitry that can correct for an incorrect bit

during this time. The user should initiate the busy indicator if

desired during this time. It is also possible to corrupt the sample

by having SCK or SDI transitions near the sampling instant.

Therefore, it is recommended to keep the digital pins quiet for

approximately 30 ns before and 10 ns after the rising edge of

CNV. The exception is when the device is in the chain mode

with busy configuration, where SDI is tied to CNV, because this

scenario does not yield a corrupted sample. To this extent, it is

recommended, to use a discontinuous SCK whenever possible to

avoid any potential performance degradation.

Rev. B | Page 16 of 24

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