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AD7982 Datasheet(PDF) 21 Page - Analog Devices |
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AD7982 Datasheet(HTML) 21 Page - Analog Devices |
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21 / 26 page ![]() AD7982 Data Sheet Rev. D | Page 20 of 25 CS MODE, 4-WIRE WITHOUT BUSY INDICATOR CS mode, 4-wire without busy indicator is usually used when multiple AD7982 devices are connected to an SPI-compatible digital host. A connection diagram example using two AD7982 devices is shown in Figure 33, and the corresponding timing is given in Figure 34. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. If SDI and CNV are low, SDO is driven low. Prior to the minimum conversion time, SDI can select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion completes, the AD7982 enters the acquisition phase and powers down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 18th SCK falling edge or when SDI goes high (whichever occurs first), SDO returns to high impedance and another AD7982 can be read. AD7982 SDI SDO CNV SCK CONVERT DATA IN CLK DIGITAL HOST CS1 CS2 AD7982 SDI SDO CNV SCK Figure 33. CS Mode, 4-Wire Without Busy Indicator Connection Diagram SDO D17 D16 D15 D1 D0 tDIS SCK 12 3 34 35 36 tHSDO tDSDO tEN CONVERSION ACQUISITION tCONV tCYC tACQ ACQUISITION SDI(CS1) CNV tSSDICNV tHSDICNV D1 16 17 tSCK tSCKL tSCKH D0 D17 D16 19 20 18 SDI(CS2) Figure 34. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing |
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