AD5040/5060

Preliminary Technical Data

Rev. PrC | Page 6 of 17

PIN CONFIGURATION AND FUNCTION

DESCRIPTION

Figure 2. AD5063 8 ld SOT23

Table 2. Pin Function Descriptions

Mnemonic

Function

REF

Reference Voltage Input.

DacGND

Ground input to the DAC.

Analog output voltage from DAC.

SYNC

Level triggered control input (active low). This is the frame synchronization signal for the input data. When

SYNC goes low,

it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated

following the 16th clock cycle unless

SYNC is taken high before this edge in which case the rising edge of SYNC acts as an

interrupt and the write sequence is ignored by the DAC.

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be

transferred at rates up to 30 MHz.

Serial Data Input. This device has a 24 bit shift register. Data is clocked into the register on the falling edge of the serial clock

input.

AGND

Ground reference point for Analog circuitry on the part.