AD5040/5060

Preliminary Technical Data

Rev. PrC | Page 4 of 17

TIMING CHARACTERISTICS

(VDD = 2.7-5.5 V; all specifications TMIN to TMAX unless otherwise noted)

Parameter

Unit

Test Conditions/Comments

3

33

ns min

SCLK Cycle Time

13

ns min

SCLK High Time

12

ns min

SCLK Low Time

13

ns min

SYNC to SCLK Falling Edge Setup Time

5

ns min

Data Setup Time

4.5

ns min

Data Hold Time

0

ns min

SCLK Falling Edge to

SYNC Rising Edge

33

ns min

Minimum

SYNC High Time

13

ns min

SYNC Rising Edge to next SCLK Fall

Ignore

.

NOTES

1All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2See Figure 1.

3Maximum SCLK frequency is 30 MHz.

Specifications subject to change without notice.

Figure 1. Timing DiagramAD506. AD5040 has same timing specs with 14 bit Word.