AD9925 datasheet(18/96 Pages) AD

18 / 96 page

AD9925

Rev. A | Page 18 of 96

P[48] = P[0]

P[24]

P[36]

NOTES

1. DATA OUTPUT (DOUT) AND DCLK PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.

2. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.

3. OUTPUT DELAY (

tOD) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.

P[0]

P[12]

PIXEL

PERIOD

DOUT

DCLK

tOD

Figure 21. Digital Output Phase Adjustment

E = 0.

FT DOUT TRA

HICH IS EQ

FOR THE DOUTPHASE LOCATION.

SHPLOC EDGE OR THE 11 EDGES FOLLOWING SHPLOC.

ECOMMENDED VALUE FOR

tOD (DOUT DLY) IS 4ns.

SING REGISTER 0x03, BIT [4] = 1, SO THAT THE ADC DATA OUTPUTS APPEAR DIRECTLY AT THE

ECOMMENDED IF ADJUSTABLE DOUT PHASE IS NOT REQUIRED.

NOTES

1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMOD

2. HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHI

3. INHIBIT TIME FOR DOUT PHASE IS DEFINED BY tDOUTINH, W

11 EDGE LOCATIONS FOLLOWING SHDLOC NOT BE USED

4. RECOMMENDED VALUE FOR DOUT PHASE IS TO USE THE

5. R

NSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.

UAL TO SHDLOC PLUS 11 EDGES. IT IS RECOMMENDED THAT THE

6. THE DOUT LATCH CAN BE BYPASSED U

DOUT PINS. THIS CONFIGURATION IS R

DCLK

DOUT

N – 13

N– 8

N– 9

N – 10

N – 11

N – 12

CCDIN

SHD

(INTERNAL)

N + 1

N + 2

N + 4

N + 3

CLI

N + 12

N + 11

N + 10

N + 9

N + 8

N + 7

N + 13

N +

N + 5

N– 7

N– 3

N– 4

N– 5

– 6

N– 2

N– 1

N + 1

SAMPLE PIXEL N

tCLIDLY

N– 1

PIPELINE LATENC

tDOUTINH

Y = 11 CYCLES

N + 2

N – 13

N– 8

N– 9

N – 10

N – 11

N – 12

N– 3

N– 4

N– 5

N– 2

N– 1

N + 1

N + 2

N– 6

N– 7

ADC DOUT

(INTERNAL)

Figure

utput Pipeline Delay

ONTAL

tal cl

lses

programmable to suit a variety of applications. Individu

trol is provided for CLPOB, PBLK, and HBLK during th

d. Th

e dark pixel clam

and blanking patterns to be changed at each stage of the

out, which accommodates the different image transfer t

and high speed line shifts.

Individual CLPOB and PBLK Patterns

he AFE horizontal timing consists of CLPOB and PBLK, as

wn in Figure 23. These two signals are independently pro-

rammed using the registers in Table 10. SPOL is the start po-

larity for the signal, and TOG1 and TOG2 are the first and sec-

ond toggle positions of the pulse. Both signals ar

and should be programmed accordingly.

te vertical sequences

be changed accordingly with

each change in the vertical timing.

CLPOB Masking Area

Additionally, the AD9925 allows the CLPOB signal to be dis-

abled during certain lines in the field without changing any of

B pattern settings. There are two ways to use

CLPOB masking. First, the six CLPOBMASK registers can be used

22. Digital Data O

HORIZ

CLAM ING AND BLANKING

The AD9925’s

rizon

amping and blanking pu

are fully

al con-

e differ-

A separate pattern for CLPOB and PBLK may be programmed

for every 10 vertical sequences. As described in the Vertical

Timing Generation section, up to 10 separa

ent regions of each fiel

is allows th

ping

read-

iming

can be created, each containing a unique pulse pattern for

CLPOB and PBLK. Figure 37 shows how the sequence change

positions divide the readout field into different regions. A dif-

ferent vertical sequence can be assigned to each region, allowing

the CLPOB and PBLK signals to

sho

e active low

the existing CLPO

AD9925 Datasheet(PDF) 18 Page - Analog Devices

AD9925 Datasheet(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL