AD7623

Rev. 0 | Page 8 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44

39 38 37

43 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

AGND

CNVST

PD

RESET

CS

RD

DGND

AGND

AVDD

NC

BYTESWAP

OB/2C

NC = NO CONNECT

SER/PAR

D0

D1

D2/DIVSCLK[0]

BUSY

D15

D14

D13

AD7623

D3/DIVSCLK[1]

D12

DGND

DGND

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

1, 41, 42

AGND

P

Analog Power Ground Pin.

2, 44

AVDD

P

Input Analog Power Pins. Nominally 2.5 V.

3, 40

NC

No Connect.

4

BYTESWAP

DI

Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output

on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].

5

OB/2C

DI

Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary;

when low, the MSB is inverted resulting in a twos complement output from its internal shift register.

6, 7

DGND

P

Digital Power Ground.

8

SER/PAR

DI

Serial/Parallel Selection Input. When high, the serial interface is selected and some bits of the data bus

are used as a serial port; the remaining data bits are high impedance outputs. When SER/PAR = low,

the parallel port is selected.

9, 10

D[0:1]

DO

Bit 0 and Bit 1 of the Parallel Port Data Output Bus.

11, 12

D[2:3]

DI/O

When SER/PAR = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.

or

DIVSCLK[0:1]

When SER/PAR = high, serial clock division selection. When using serial master read after convert

mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally

generated serial clock that clocks the data output. In other serial modes, these pins are high

impedance outputs.

13

D4

DI/O

When SER/PAR = low, this output is used as Bit 4 of the parallel port data output bus.

or EXT/INT

When SER/PAR = high, serial clock source select. This input is used to select the internally generated

(master ) or external (slave) serial data clock.

When EXT/INT = low, master mode. The internal serial clock is selected on SCLK output.

When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal, gated

by CS, connected to the SCLK input.

14

D5

DI/O

When SER/PAR = low, this output is used as Bit 5 of the parallel port data output bus.

or INVSYNC

When SER/PAR = high, invert sync select. In serial master mode (EXT/INT = low), this input is used to

select the active state of the SYNC signal.

When INVSYNC = low, SYNC is active high.

When INVSYNC = high, SYNC is active low.

15

D6

DI/O

When SER/PAR = low, this output is used as Bit 6 of the parallel port data output bus.

or INVSCLK

Invert SCLK Select. In all serial modes, this input is used to invert the SCLK signal.