AD7623AST datasheet(25/29 Pages) AD

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AD7623

Rev. 0 | Page 24 of 28

SLAVE SERIAL INTERFACE

External Clock

The AD7623 is configured to accept an externally supplied

serial data clock on the SCLK pin when the EXT/INT pin is

held high. In this mode, several methods can be used to read

the data. The external serial clock is gated by CS. When CS and

RD are both low, the data can be read after each conversion or

during the following conversion. The external clock can be

either a continuous or a discontinuous clock. A discontinuous

clock can be either normally high or normally low when

inactive. Figure 40 and Figure 41 show the detailed timing

diagrams of these methods.

While the AD7623 is performing a bit decision, it is important

that voltage transients be avoided on digital input/output pins,

or degradation of the conversion result could occur. This is

particularly important during the second half of the conversion

phase because the AD7623 provides error correction circuitry

that can correct for an improper bit decision made during the

first half of the conversion phase. For this reason, it is recom-

mended that when an external clock is being provided, it is a

discontinuous clock that is toggling only when BUSY is low or,

more importantly, that it does not transition during the latter

half of BUSY high.

External Discontinuous Clock Data Read After

Conversion

Though the maximum throughput cannot be achieved using

this mode, it is the most recommended of the serial slave

modes. Figure 40 shows the detailed timing diagrams of this

method. After a conversion is complete, indicated by BUSY

returning low, the conversion result can be read while both CS

and RD are low. Data is shifted out MSB first with 16 clock

pulses and is valid on the rising and falling edges of the clock.

One advantage of this method is that conversion performance

is not degraded because there are no voltage transients on the

digital interface during the conversion process. Another

advantage is the ability to read the data at any speed up to

80 MHz, which accommodates both the slow digital host

interface and the fastest serial reading.

Finally, in this mode only, the AD7623 provides a daisy-chain

feature using the RDC/SDIN pin for cascading multiple con-

verters together. This feature is useful for reducing component

count and wiring connections when desired, as, for instance, in

isolated multiconverter applications.

An example of the concatenation of two devices is shown in

Figure 39. Simultaneous sampling is possible by using a

common CNVST signal. It should be noted that the RDC/SDIN

input is latched on the edge of SCLK opposite to the one used to

shift out the data on SDOUT. Hence, the MSB of the upstream

converter just follows the LSB of the downstream converter on

the next SCLK cycle.

SCLK

SDOUT

RDC/SDIN

AD7623

(DOWNSTREAM)

AD7623

(UPSTREAM)

BUSY

OUT

BUSY

DATA

OUT

SCLK

RDC/SDIN

SDOUT

SCLK IN

CNVST IN

CNVST

CS IN

Figure 39. Two AD7623 Devices in a Daisy-Chain Configuration

External Clock Data Read During Previous Conversion

Figure 41 shows the detailed timing diagrams of this method.

During a conversion, while both CS and RD are low, the result

of the previous conversion can be read. The data is shifted out,

MSB first, with 16 clock pulses, and is valid on both the rising

and falling edge of the clock. The 16 bits have to be read before

the current conversion is complete; otherwise, RDERROR is

pulsed high and can be used to interrupt the host interface to

prevent incomplete data reading. There is no daisy-chain

feature in this mode, and RDC/SDIN input should always be

tied either high or low.

To reduce performance degradation due to digital activity, a fast

discontinuous clock of at least 40 MHz is recommended to

ensure that all the bits are read during the first half of the SAR

conversion phase.

It is also possible to begin to read data after conversion and

continue to read the last bits after a new conversion has been

initiated.

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