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Data Sheet

AD7265

Rev. B | Page 17 of 28

ANALOG INPUT SELECTION

The analog inputs of the AD7265 can be configured as single-

ended or true differential via the SGL/DIFF logic pin, as shown

in Figure 31. If this pin is tied to a logic low, the analog input

channels to each on-chip ADC are set up as three true differen-

tial pairs. If this pin is at logic high, the analog input channels to

each on-chip ADC are set up as six single-ended analog inputs.

The required logic level on this pin needs to be established prior

to the acquisition time and remain unchanged during the con-

version time until the track-and-hold has returned to track. The

track-and-hold returns to track on the 13th rising edge of SCLK

after the CS falling edge (see Figure 41). If the level on this pin

is changed, it is recognized by the AD7265; therefore, it is

necessary to keep the same logic level during acquisition and

conversion to avoid corrupting the conversion in progress.

For example, in Figure 31, the SGL/DIFF pin is set at logic high

for the duration of both the acquisition and conversion times

so the analog inputs are configured as single ended for that

conversion (Sampling Point A). The logic level of the SGL/DIFF

changed to low after the track-and-hold returned to track and

prior to the required acquisition time for the next sampling

instant at Point B; therefore, the analog inputs are configured as

differential for that conversion.

SCLK

114

SGL/DIFF

tACQ

Figure 31. Selecting Differential or Single-Ended Configuration

The channels used for simultaneous conversions are selected via

the multiplexer address input pins, A0 to A2. The logic states of

these pins also need to be established prior to the acquisition

time; however, they may change during the conversion time,

provided that the mode is not changed. If the mode is changed

from fully differential to pseudo-differential, for example, then

the acquisition time would start again from this point. The

selected input channels are decoded as shown in Table 6.

The analog input range of the AD7265 can be selected as 0 V to

VREF or 0 V to 2 × VREF via the RANGE pin. This selection is

made in a similar fashion to that of the SGL/DIFF pin by setting

the logic state of the RANGE pin a time tacq prior to the falling

edge of CS. Subsequent to this, the logic level on this pin can be

altered after the third falling edge of SCLK. If this pin is tied to a

logic low, the analog input range selected is 0 V to VREF. If this

pin is tied to a logic high, the analog input range selected is 0 V

to 2 × VREF.

OUTPUT CODING

The AD7265 output coding is set to either twos complement or

straight binary, depending on which analog input configuration

is selected for a conversion. Table 5 shows which output coding

scheme is used for each possible analog input configuration.

Table 5. AD7265 Output Coding

SGL/DIFF

Range

Output Coding

DIFF

0 V to VREF

Twos complement

DIFF

0 V to 2 × VREF

Twos complement

SGL

0 V to VREF

Straight binary

SGL

0 V to 2 × VREF

Twos complement

PSEUDO DIFF

0 V to VREF

Straight binary

PSEUDO DIFF

0 V to 2 × VREF

Twos complement

Table 6. Analog Input Type and Channel Selection

ADC A

ADC B

SGL/DIFF

VIN+

VIN−

VIN+

VIN−

Comment

VA1

AGND

VB1

AGND

Single ended

VA2

AGND

VB2

AGND

Single ended

VA3

AGND

VB3

AGND

Single ended

VA4

AGND

VB4

AGND

Single ended

VA5

AGND

VB5

AGND

Single ended

VA6

AGND

VB6

AGND

Single ended

VA1

VA2

VB1

VB2

Fully differential

VA1

VA2

VB1

VB2

Pseudo differential

VA3

VA4

VB3

VB4

Fully differential

VA3

VA4

VB3

VB4

Pseudo differential

VA5

VA6

VB5

VB6

Fully differential

VA5

VA6

VB5

VB6

Pseudo differential

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