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CP3UB17 Datasheet(PDF) 49 Page - National Semiconductor (TI) |
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CP3UB17 Datasheet(HTML) 49 Page - National Semiconductor (TI) |
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49 / 200 page  49 www.national.com All reserved or unused interrupt vectors should point to a default or error interrupt handlers. 10.5 NESTED INTERRUPTS Nested NMI interrupts are always enabled. Nested maskable interrupts are disabled by default, however an in- terrupt handler can allow nested maskable interrupts by set- ting the I bit in the PSR. The LPR instruction is used to set the I bit. Nesting of specific maskable interrupts can be allowed by disabling interrupts from sources for which nesting is not al- lowed, before setting the I bit. Individual maskable interrupt sources can be disabled using the IENAM0 and IENAM1 registers. Any number of levels of nested interrupts are allowed, limit- ed only by the available memory for the interrupt stack. |
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