CP3UB17 datasheet(12/200 Pages) NSC

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4.1

PIN DESCRIPTION

Some pins may be enabled as general-purpose I/O-port

pins or as alternate functions associated with specific pe-

ripherals or interfaces. These pins may be individually con-

figured as port pins, even when the associated peripheral or

interface is enabled. Table 4 lists the device pins.

Table 4

CP3UB17 Pin Description for the 100-Pin LQFP Package

Name

Pins

I/O

Primary Function

Alternate

Name

Alternate Function

X1CKI

Input

12 MHz Oscillator Input

None

X1CKO

Output

12 MHz Oscillator Output

None

X2CKI

Input

32 kHz Oscillator Input

None

X2CKO

Output

32 kHz Oscillator Output

None

AVCC

Input

PLL Analog Power Supply

None

IOVCC

Input

2.5V - 3.3V I/O Power Supply

None

VCC

Input

2.5V Core Logic

Power Supply

None

GND

Input

Reference Ground

None

AGND

Input

PLL Analog Ground

None

RESET

Input

Chip general reset

None

TMS

Input

JTAG Test Mode Select

(with internal weak pull-up)

None

TDI

Input

JTAG Test Data Input

(with internal weak pull-up)

None

TDO

Output

JTAG Test Data Output

None

TCK

Input

JTAG Test Clock Input

(with internal weak pull-up)

None

RDY

Output

NEXUS Ready Output

None

PG0

I/O

Generic I/O

RXD

UART Receive Data Input

WUI10

Multi-Input Wake-Up Channel 10

PG1

I/O

Generic I/O

TXD

UART Transmit Data Output

WUI11

Multi-Input Wake-Up Channel 11

PG2

I/O

Generic I/O

RTS

UART Ready-To-Send Output

WUI12

Multi-Input Wake-Up Channel 12

PG3

I/O

Generic I/O

CTS

UART Clear-To-Send Input

WUI13

Multi-Input Wake-Up Channel 13

PG5

I/O

Generic I/O

SRFS

AAI Receive Frame Sync

NMI

Non-Maskable Interrupt Input

PH0

I/O

Generic I/O

MSK

SPI Shift Clock

TIO1

Versatile Timer Channel 1

PH1

I/O

Generic I/O

MDIDO

SPI Master In Slave Out

TIO2

Versatile Timer Channel 2

PH2

I/O

Generic I/O

MDODI

SPI Master Out Slave In

TIO3

Versatile Timer Channel 3

CP3UB17 Datasheet(PDF) 12 Page - National Semiconductor (TI)

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