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AD7923

Data Sheet

Rev. D | Page 20 of 24

For example, if the AD7923 is operated in a continuous samp-

ling mode, with a throughput rate of 200 kSPS and an SCLK of

20 MHz (AVDD = 5 V), and the device is placed in auto shut-

down mode, that is, if PM1 = 0 and PM0 = 1, then the power

consumption is calculated as follows:

The maximum power dissipation during conversion is 13.5 mW

(IDD = 2.7 mA max, AVDD = 5 V). If the power-up time from auto

shutdown is one dummy cycle, that is 1 µs, and the remaining

conversion time is another cycle, that is, 800 ns, then the

AD7923 can be said to dissipate 13.5 mW for 1.8 µs during each

conversion cycle. For the remainder of the conversion cycle,

3.2 µs, the part remains in shutdown. The AD7923 can be said

to dissipate 2.5 µW for the remaining 3.2 µs of the conver-sion

cycle. If the throughput rate is 200 kSPS, the cycle time is

5 µs and the average power dissipated during each cycle is

(1.8/5) × (13.5 mW) + (3.2/5) × (2.5 µW) = 4.8616 mW.

Figure 26 shows the maximum power vs. throughput rate when

using the auto shutdown mode with 5 V and 3 V supplies.

THROUGHPUT (kSPS)

0.1

0.01

100

180

160

140

120

100

AVDD = 5V

AVDD = 3V

Figure 26. Power vs. Throughput Rate

SERIAL INTERFACE

Figure 27 shows the detailed timing diagrams for serial inter-

facing to the AD7923. The serial clock provides the conversion

clock and controls the transfer of information to and from the

AD7923 during each conversion.

The CS signal initiates the data transfer and conversion process.

The falling edge of CS puts the track-and-hold into hold mode

and takes the bus out of three-state; the analog input is sampled

at this point. The conversion is also initiated at this point and

requires 16 SCLK cycles to complete. The track-and-hold returns

to track mode at Point B on the 14th SCLK falling edge, as

shown in Figure 27. On the 16th SCLK falling edge the DOUT

line returns to three-state. If the rising edge of CS occurs before

16 SCLKs have elapsed, the conversion is terminated, the DOUT

line returns to three-state, and the control register is not updated;

otherwise DOUT returns to three-state on the 16th SCLK

falling edge, as shown in Figure 27.

Sixteen serial clock cycles are required to perform the conver-

sion process and to access data from the AD7923. For the

AD7923, the 12 bits of data are preceded by two leading 0s and

Channel Address Bits ADD1 and ADD0, identifying which

channel the result corresponds to. CS going low clocks out the

first leading 0 to be read by the microcontroller or DSP on the

first falling edge of SCLK. The first falling edge of SCLK also

clocks out the second leading 0 to be read by the microcon-

troller or DSP on the second SCLK falling edge, and so on. The

remaining two address bits and 12 data bits are then clocked out

by subsequent SCLK falling edges, beginning with the first

Address Bit ADD1, thus the second falling clock edge on the

serial clock has the second leading 0 and also clocks out

Address Bit ADD1. The final bit in the data transfer is valid on

the 16th falling edge, having been clocked out on the previous

(15th) falling edge.

Writing information to the control register takes place on the

first 12 falling edges of SCLK in a data transfer, assuming the

MSB, that is, the write bit, has been set to 1.

The 16-bit word read from the AD7923 always contain two

leading 0s, two channel address bits that the conversion result

corresponds to, followed by the 12-bit conversion result.

Writing Between Conversions

As outlined in the operating modes section, not less than 5 µs

should be left between consecutive valid conversions. There is

one exception, however: consider the case when writing to the

AD7923 to power it up from shutdown prior to a valid conver-

sion. The user must write to the part to tell it to power up before

it can convert successfully. Once the serial write to power up

has finished, the user might want to perform the conversion as

soon as possible without waiting an additional 5 µs before

bringing CS low for the conversion. In this case, as long as there

is a minimum of 5 µs between each valid conversion, only the

quiet time between the CS rising edge at the end of the write to

power up and the next CS falling edge needs to be met.

Figure 28 illustrates this point. Note that when writing to the

AD7923 between these valid conversions, the DOUT line is not

driven during the extra write operation.

It is critical that an extra write operation as outlined above is

never issued between valid conversions when the AD7923 is

executing a sequence function, because the falling edge of CS in

the extra write moves the mux to the next channel in the

sequence. This means that when the next valid conversion takes

place a channel result would be missed.

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