MB91F128 datasheet(3/50 Pages) FUJITSU

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MB91F127/F128

(Continued)

Other interval timers

• 16-bit timer : 3 channels (U-Timer)

• PPG timer : 4 channels

• 16-bit OCU : 4 channels, ICU : 4 channels, Free-run timer : 1 channel

• Watchdog timer: 1 channel

Flash memory 510 KB

• 510 KB FLASH ROM: Read/Write/Erase is allowed with a same power

Built- in RAM 14 KB

• D-bus RAM 12 KB, C-bus RAM 2 KB

Bit search module

• Position of a first bit that changes between “1” and “0” is searched in one cycle, within an MSB of one word.

Interrupt controller

• External interrupt input : Normal interrupt

×6 (INT0 to INT5)

• Internal interrupt factors : UART, DMAC, A/D, Reload timer, UTIMER, delay interrupt, PPG, ICU, and OCU

• Priority levels are programmable (16 levels)

Reset factors

• Power-on reset/watchdog timer/software reset/external reset

Low power consumption mode

• Sleep/stop mode

Clock control

• Built-in PLL circuit, selectable among 1-multiplication, and 2-multiplication

• Gearing function : Operation clock frequencies are freely and independently specifiable for CPU and

peripherals.

Gear clocks are selectable among 1/1, 1/2, 1/4, and 1/8 (or among 1/2, 1/4, 1/8, and 1/16).

Upper limit of peripheral operations is 25 MHz.

Others

• Package : LQFP-100

• CMOS technology : 0.35

µm

• Power supply voltage : 3.3 V

±0.3 V

s SERIES CONFIGURATION

Model name

MB91F127

MB91F128

MB91FV129

Outline

Quantity production

Evaluation product

FLASH memory

256 KB

510 KB

D-bus RAM

12 KB

16 KB

C-bus RAM

2 KB

MB91F128 Datasheet(PDF) 3 Page - fujitsu semiconductor

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