AD7677ACPRL datasheet(12/21 Pages) AD

12 / 21 page

REV. A

AD7677

–11–

TEMPERATURE – C

250

100

–15

105

–55

150

DVDD

–35

200

OVDD

AVDD

TPC 13. Power-Down Operating Currents vs. Temperature

CIRCUIT INFORMATION

The AD7677 is a very fast, low power, single-supply, precise,

16-bit analog-to-digital converter (ADC). The AD7677 features

different modes to optimize performances according to the

applications.

In Warp Mode, the AD7677 is capable of converting 1,000,000

samples per second (1 MSPS).

The AD7677 provides the user with an on-chip track/hold,

successive approximation ADC that does not exhibit any pipe-

line or latency, making it ideal for multiple multiplexed channel

applications.

The AD7677 can be operated from a single 5 V supply and

be interfaced to either 5 V or 3 V digital logic. It is housed in a

48-lead LQFP package that combines space savings and flexible

configurations as either serial or parallel interface. The AD7677

is a pin-to-pin compatible upgrade of the AD7664, AD7675,

and AD7676.

CONVERTER OPERATION

The AD7677 is a successive approximation analog-to-digital

converter based on a charge redistribution DAC. Figure 3 shows

the simplified schematic of the ADC. The capacitive DAC con-

sists of two identical arrays of 16 binary weighted capacitors

that are connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

comparator’s input are connected to AGND via SW+ and SW–.

All independent switches are connected to the analog inputs.

Thus, the capacitor arrays are used as sampling capacitors and

acquire the analog signal on IN+ and IN– inputs. When the

acquisition phase is complete and the

CNVST input goes

low, a conversion phase is initiated. When the conversion phase

begins, SW+ and SW– are opened first. The two capacitor arrays

are then disconnected from the inputs and connected to the

REFGND input. Therefore, the differential voltage between the

inputs IN+ and IN– captured at the end of the acquisition phase

is applied to the comparator inputs, causing the comparator to

become unbalanced. By switching each element of the capacitor

array between REFGND or REF, the comparator input varies

by binary weighted voltage steps (VREF/2, VREF/4 . . . VREF/65536).

The control logic toggles these switches, starting with the MSB

first, in order to bring the comparator back into a balanced

condition. After the completion of this process, the control logic

generates the ADC output code and brings BUSY output low.

Modes of Operation

The AD7677 features three modes of operations, Warp, Normal,

and Impulse. Each of these modes is more suitable for specific

applications.

IN+

REF

REFGND

IN–

32,768C 16,384C

MSB

LSB

SW+

SWITCHES

CONTROL

32,768C 16,384C

MSB

LSB

SW–

BUSY

OUTPUT

CODE

CNVST

CONTROL

LOGIC

COMP

Figure 3. ADC Simplified Schematic

TEMPERATURE – C

–5

–55

135

–35

–15

–5

–1

–3

115

–2

–4

–FS

OFFSET

+FS

TPC 14. Drift vs. Temperature

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