PNX2000 datasheet(21/31 Pages) PHILIPS

21 / 31 page

9397 750 13928

Product data

Rev. 03 – 23 August 2004

21 of 31

Philips Semiconductors

PNX2000

Audio video input processor

[1]

Allowed SCK/WS ratios are 32, 48, 64, 128 and 256 SCK periods per WS period.

[2]

All timings relative to the rising edge of SCK.

[3]

See Section 10.4 for waveforms.

th(DATA)

data hold at Rx

40 pF load

4.9

I2S

audio sample frequency

kHz

fSCK

SCK frequency

I2S-bus master mode

64fs

fSCK

SCK frequency

I2S-bus slave mode

32fs

64fs

256fs

DFSCK

SCK duty factor

I2S-bus master mode

DFSCK

SCK duty factor

I2S-bus slave mode

tRSCK

SCK rise / fall time

I2S-bus master mode; Cload = 30 pF

tRSCK

SCK rise / fall time

I2S-bus slave mode; fSCK = 3.072 MHz -

delay time: SCK to WS and SD

outputs [2]

TSCK = 1/fSCK

0.3

0.5

0.7

TSCK

hold time: SCK to WS and SD inputs -

setup time: WS and SD inputs to

SCK

TSCK = 1/fSCK

0.2

TSCK

I2D

fclock(WORD) word clock frequency

13.5

MHz

word length

bit

data rate

594

Mbit/s

fclock(BIT)

bit clock freq.

297

MHz

JTAG Clock Reset

tlow

Time RESET_N should be below

Vtrip_high before internal reset = 1.

RESET_SEL = 0

µs

thigh

Time RESET_N should be above

Vtrip_high before internal reset = 0

(after tpulse).

RESET_SEL = 0

µs

tpulse

Time before PNX2000 internal reset

= 0 [3].

RESET_SEL = 0

200

Table 23:

Dynamic characteristics…continued

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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