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AD7864

Rev. D | Page 16 of 28

logic high). The pointer is incremented to point to the next

available. Thus, FRSTDATA in Figure 9 is shown as going low

just prior to the second EOC pulse. Repeated read operations

during a conversion continue to access the data at the current

pointer location until the pointer is incremented at the end of

that conversion. Note that FRSTDATA has an indeterminate

logic state after initial power-up. This means that for the first

conversion sequence after power-up, the FRSTDATA logic

output may already be logic high before the end of the first

conversion (this condition is indicated by the dashed line in

). Also, the FRSTDATA logic output may already be

high as a result of the previous read sequence, as is the case after

the fourth read in

. The fourth read (rising edge of

Figure 9

RD)

resets the pointer to the first data location. Therefore, FRSTDATA

is already high when the next conversion sequence initiates. See

the

section.

Accessing the Output Data Registers

Reading After the Conversion Sequence

Figure 10 shows the same conversion sequence as Figure 9. In

this case, however, the results of the four conversions (on VIN1 to

VIN4) are read after all conversions have finished, that is, when

BUSY goes logic low. The FRSTDATA signal goes logic high at

the end of the first conversion just prior to EOC going logic low.

As mentioned previously, FRSTDATA has an indeterminate

state after initial power-up, therefore FRSTDATA may already

be logic high. Unlike the case when reading between each

conversion, the output data register pointer is incremented on

the rising edge of RD because the next conversion result is

available. This means FRSTDATA goes logic low after the first

rising edge on RD.

tBUSY

QUIET

TIME

t12

VIN1

VIN2

VIN3

VIN4

100ns

DATA

CONVST

BUSY

EOC

FRSTDATA

H/S SEL

SL1 TO SL4

tCONV

tACQ

t11

t10

tCONV

Figure 9. Timing Diagram for Reading During Conversion

t10

QUIET

TIME

DATA

CONVST

BUSY

EOC

FRSTDATA

VIN1

VIN2

VIN3

VIN4

VIN1

tBUSY

t10

Figure 10. Timing Diagram, Reading After the Conversion Sequence

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