AD7864 datasheet(18/29 Pages) AD

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AD7864

Rev. D | Page 17 of 28

Successive read operations access the remaining conversion

results in an ascending channel order. Each read operation

increments the output data register pointer. The read operation

that accesses the last conversion result causes the output data

the first conversion result again. This is shown in Figure 10,

wherein the fifth read after BUSY goes low accessing the result

of the conversion on VIN1. Thus, the output data registers act as

a circular buffer in which the conversion results are continually

accessible. The FRSTDATA signal goes high when the first

conversion result is available.

Data is enabled onto the data bus (DB0 to DB11) using CS and

RD. Both CS and RD have the same functionality as described

in the previous section. There are no restrictions or performance

implications associated with the position of the read operations

after BUSY goes low. The only restriction is that there is minimum

time between read operations. Notice that the quiet time must

be allowed before the start of the next conversion.

USING AN EXTERNAL CLOCK

The logic input INT/EXT CLK allows the user to operate the

AD7864 using the internal clock oscillator or an external clock.

To achieve optimum performance on the AD7864, use the internal

clock. The highest external clock frequency allowed is 5 MHz.

This means a conversion time of 2.6 μs compared to 1.65 μs

when using the internal clock. In some instances, however, it

may be useful to use an external clock when high throughput

rates are not required. For example, two or more AD7864s can

be synchronized by using the same external clock for all

devices. In this way, there is no latency between output logic

signals like EOC due to differences in the frequency of the

internal clock oscillators.

shows how the various logic

outputs are synchronized to the CLK signal. Each conversion

requires 14 clocks. The output data register pointer is reset to

point to the first register location on the falling edge of the 12th

clock cycle of the first conversion in the conversion sequence—

see the

section. At this

point, the logic output FRSTDATA goes logic high. The result of

the first conversion transfers to the output data registers on the

falling edge of the 13th clock cycle. The FRSTDATA signal is

reset on the falling edge of the 13th clock cycle of the next

conversion, that is, when the result of the second conversion is

transferred to its output data register. As mentioned previously,

the pointer is incremented by the rising edge of the

Figure 11

Accessing the Output Data Registers

RD signal if

the result of the next conversion is available. The EOC signal

goes logic low on the falling edge of the 13th clock cycle and is

reset high again on the falling edge of the 14th clock cycle.

CONVST

BUSY

EOC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 45 6 7 89 10 11 12 13 14 1 213 14

CLK

FRSTDATA

FIRST CONVERSION

COMPLETE

LAST CONVERSION

COMPLETE

Figure 11. Using an External Clock

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