TLV5734

TRIPLE 8BIT 30MSPS ADC WITH HIGH

PRECISION CLAMP FOR YUV/RGB VIDEO

SLES026A – APRIL 2002 – REVISED JANUARY 2003

6

POST OFFICE BOX 655303

detailed description

ADC

The TLV5734 includes three 8-bit A/D channels. Each ADC employs a three-stage switched capacitor-pipelined

architecture to achieve high accuracy and high throughput with low power consumption. The analog input is

sampled when the external clock, CLK, goes from low to high. The INIT signal is used to initialize the order of

output data when operating in the 4:2:2 or 4:1:1 output format mode. After INIT changes from low to high, the

first reinitialized output data is available after a 5-clock-cycle delay from the rising edge of the CLK (see the

timing diagram, Figure 1).

Pulling the OEB pin (pin 4, 27 or 34) high puts the corresponding ADC output in the high-impedance state.

tw(H)

tw(L)

N–2

CLK

INIT

Analog Input

Sampling Instance

N–1

Analog Input

Digital Output

N–7

N–1

N

N–6

N

N+1

N–5

N+1

N+2

N–4

N+2

N+3

N–3

N+3

N+4

N–2

N+4

N+5

N–1

N+5

N+6

N

N+6

N+7

N+1

N+7

tpd

Data Latency = 5 CLKs

Output Re-initialized

treset

th

tsu

Figure 1. Timing Diagram