TLV5734

TRIPLE 8BIT 30MSPS ADC WITH HIGH

PRECISION CLAMP FOR YUV/RGB VIDEO

SLES026A – APRIL 2002 – REVISED JANUARY 2003

10

POST OFFICE BOX 655303

5 CLK

tpd

CLK

A0

A1

A2

A3

A4

A5

01

23

4

5

67

89

10

11

12

–1

–2

A6

A7

INIT

OEB B

OEB A

OEB C

OUTPUT DATA A

OUTPUT DATA B

tpd

B0

B1

B2

B3

B4

B5

B6

B7

OUTPUT DATA C

tpd

C0

C1

C2

C3

C4

C5

C6

C7

Figure 5. Format 2 (4:4:4) Timing Diagram

Table 6. Output Format 2 (4:4:4)

OUTPUT DATA

CHANNEL OF ADC

BIT

CLK†

CHANNEL OF ADC

BIT

6

7

8

9

10

11

12

13

A

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

A08

A07

A06

A05

A04

A03

A02

A01

A18

A17

A16

A15

A14

A13

A12

A11

A28

A27

A26

A25

A24

A23

A22

A21

A38

A37

A36

A35

A34

A33

A32

A31

A48

A47

A46

A45

A44

A43

A42

A41

A58

A57

A56

A55

A54

A53

A52

A51

A68

A67

A66

A65

A64

A63

A62

A61

A78

A77

A76

A75

A74

A73

A72

A71

B

BD8

BD7

BD6

BD5

BD4

BD3

BD2

BD1

B08

B07

B06

B05

B04

B03

B02

B01

B18

B17

B16

B15

B14

B13

B12

B11

B28

B27

B26

B25

B24

B23

B22

B21

B38

B37

B36

B35

B34

B33

B32

B31

B48

B47

B46

B45

B44

B43

B42

B41

B58

B57

B56

B55

B54

B53

B52

B51

B68

B67

B66

B65

B64

B63

B62

B61

B78

B77

B76

B75

B74

B73

B72

B71

C

CD8

CD7

CD6

CD5

CD4

CD3

CD2

CD1

C08

C07

C06

C05

C04

C03

C02

C01

C18

C17

C16

C15

C14

C13

C12

C11

C28

C27

C26

C25

C24

C23

C22

C21

C38

C37

C36

C35

C34

C33

C32

C31

C48

C47

C46

C45

C44

C43

C42

C41

C58

C57

C56

C55

C54

C53

C52

C51

C68

C67

C66

C65

C64

C63

C62

C61

C78

C77

C76

C75

C74

C73

C72

C71

† The first ADC sampling clock is denoted as CLK 0.

A06 is an example entry in the table where A shows the ADC channel, 0 represents the sampling order, and 6 is the bit number.