TSB41BA3 datasheet(52/63 Pages) TI

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TSB41BA3

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS155A − MAY 2003 − REVISED OCTOBER 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION (1394B INTERFACE)

status transfer

A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. Two types

of status transfers may occur: bus status transfer and PHY status transfer. Bus status transfers send the

following status information: bus reset indications, subaction and arbitration reset gap indications, cycle start

indications, and PHY interface reset indications. PHY status transfers send the following information: PHY

interrupt indications, unsolicited and solicited PHY register data, bus initialization indications, and PHY-link

interface error indications. The PHY uses a different mechanism to send the bus status transfer and the PHY

status transfer.

Bus status transfers use the CTL0−CTL1 and D0−D7 terminals to transfer status information. Bus status trans-

fers can occur during idle periods on the PHY-link interface or during packet reception. When the status transfer

occurs, a single PCLK cycle of status information is sent to the LLC. The information is sent such that each indi-

vidual Dn terminal conveys a different bus status transfer event. During any bus status transfer, only one status

bit is set. If the PHY-link interface is inactive, then the status information is not sent. When a bus reset on the

serial bus occurs, the PHY sends a bus reset indication (via the CTLn and Dn terminals), cancels all packet

transfer requests, sets asynchronous and isochronous phases to even, forwards self-ID packets to the link, and

sends an unsolicited PHY register 0 status transfer (via the PINT terminal) to the LLC. In the case of a PHY

interface reset operation, the PHY-link interface is reset on the following PCLK cycle.

Table 33 shows the definition of the bits during the bus status transfer and Figure 24 shows the timing.

Table 33. Status Bits

STATUS BIT

DESCRIPTION

Bus reset

Arbitration reset gap—Odd

Arbitration reset gap—Even

Cycle start—Odd

Cycle start—Even

Subaction gap

PHY interface reset

Reserved

D[0:7]

CTL[0:1]

Status Bits

Figure 24. Bus Status Transfer Timing

TSB41BA3 Datasheet(PDF) 52 Page - Texas Instruments