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TSB41BA3

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS155A − MAY 2003 − REVISED OCTOBER 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

power-up reset

To ensure proper operation of the TSB41BA3 the RESETz terminal must be asserted low for a minimum of 2 ms

from the time that PHY power reaches the minimum required supply voltage and the input clock to the PHY is

valid. When using a passive capacitor on the RESETz terminal to generate a power-on reset signal, the

minimum reset time is assured if the value of the capacitor satisfies the following equation (the value must be

no smaller than approximately 0.1

µF):

Cmin = 0.0077 * T + 0.085 + (external_oscillator_start−up_time * 0.05)

Where Cmin is the minimum capacitance on the RESETz terminal in µF, T is the VDD ramp time, 10%–90%, in

ms, external_oscillator_start−up_time is the time from power applied to the external oscillator until the oscillator

outputs a valid clock in ms. If a crystal is used rather than an oscillator, then the external_oscillator_start-up_time

may be set to 0.

For example with a 2−ms power ramp time and a 2-ms oscillator startup time:

Cmin = 0.0077 * 2 + 0.085 + (2 * 0.05) = 0.2 µF

It is appropriate to select the nearest standard value capacitor that exceeds this value, for example 0.22

µF.

Or with a 2-ms power ramp time and a 49.152-MHz fundamental crystal:

Cmin = 0.0077 * 2 + 0.085 + (0 * 0.05) = 0.1 µF

crystal oscillator selection

The TSB41BA3 and other TI PHY devices are designed to use an external 49.152-MHz crystal connected

between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn

drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data

at the S100 through S400 media data rates.

A variation of less than

±100 ppm from nominal for the media data rates is required by IEEE Std 1394. Adjacent

PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must

be able to compensate for this difference over the maximum packet length. Larger clock variations may cause

resynchronization overflows or underflows, resulting in corrupted packet data or even PHY lockup.

For the TSB41BA3, the PCLK output may be used to measure the frequency accuracy and stability of the

internal oscillator and PLL from which it is derived. When operating the PHY-LLC interface with a non-1394b

LLC, the frequency of the PCLK output must be within

±100 ppm of the nominal frequency of 49.152 MHz. When

operating the PHY-LLC interface with a 1394b LLC, the frequency of the PCLK output must be within

±100 ppm

of the nominal frequency of 98.304 MHz.

The following are some typical specifications for crystals used with the physical layers from TI in order to achieve

the required frequency accuracy and stability:

D Crystal mode of operation: Fundamental

D Frequency tolerance at 25_C: Total frequency variation for the complete circuit is ±100 ppm. A crystal with

±30 ppm frequency tolerance is recommended for adequate margin.

D Frequency stability (over temperature and age): A crystal with ±30 ppm frequency stability is recommended

for adequate margin.

TSB41BA3 Datasheet(PDF) 29 Page - Texas Instruments

TSB41BA3 Datasheet(HTML) 29 Page - Texas Instruments

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