DS1387 datasheet(9/20 Pages) DALLAS

9 / 20 page

DS1385/DS1387

012496 9/20

REGISTERS

The DS1385/DS1387 has four control registers which

are accessible at all times, even during the update

cycle.

MSB

LSB

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

UIP

DV2

DV1

DV0

RS3

RS2

RS1

RS0

UIP – The Update In Progress (UIP) bit is a status flag

that can be monitored. When the UIP bit is a one, the

update transfer will soon occur. When UIP is a zero, the

update transfer will not occur for at least 244

µs. The

time, calendar and alarm information in RAM is fully

available for access when the UIP bit is zero. The UIP

bit is read only. Writing the SET bit in Register B to a one

inhibits any update transfer and clears the UIP status

bit.

DV2, DV1, DV0 – These three bits are used to turn the

oscillator on or off and to reset the countdown chain. A

pattern of 010 is the only combination of bits that will turn

the oscillator on and allow the RTC to keep time. A pat-

tern of 11X will enable the oscillator but holds the count-

down chain in reset. The next update will occur at 500

ms after a pattern of 010 is written to DV2, DV1, and

DV0.

RS3, RS2, RS1, RS0 – These four rate–selection bits

select one of the 13 taps on the 15–stage divider or dis-

able the divider output. The tap selected can be used to

generate an output square wave (SQW pin) and/or a pe-

riodic interrupt. The user can do one of the following:

Enable the interrupt with the PIE bit;

Enable the SQW output pin with the SQWE bit;

Enable both at the same time and the same rate; or

Enable neither.

Table 2 lists the periodic interrupt rates and the square

wave frequencies that can be chosen with the RS bits.

MSB

LSB

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

SET

PIE

AIE

UIE

SQWE

24/12

DSE

SET – When the SET bit is a zero, the update transfer

functions normally by advancing the counts once per

second. When the SET bit is written to a one, any update

transfer is inhibited and the program can initialize the

time and calendar bytes without an update occurring in

the midst of initializing. Read cycles can be executed in

a similar manner. SET is a read/write bit that is not modi-

fied by internal functions of the DS1385/DS1387.

PIE – The Periodic Interrupt Enable bit is a read/write bit

which allows the Periodic Interrupt Flag (PF) bit in Reg-

ister C to drive the IRQ pin low. When the PIE bit is set to

one, periodic interrupts are generated by driving the

IRQ pin low at a rate specified by the RS3-RS0 bits of

from being driven by a periodic interrupt, but the Period-

ic Flag (PF) bit is still set at the periodic rate. PIE is not

modified by any internal DS1385/DS1387 functions.

AIE – The Alarm Interrupt Enable (AIE) bit is a read/

write bit which, when set to a one, permits the Alarm

Flag (AF) bit in register C to assert IRQ. An alarm inter-

rupt occurs for each second that the three time bytes

equal the three alarm bytes including a don’t care alarm

code of binary 11XXXXXX. When the AIE bit is set to

zero, the AF bit does not initiate the IRQ signal. The in-

ternal functions of the DS1385/DS1387 do not affect the

AIE bit.

UIE – The Update Ended Interrupt Enable (UIE) bit is a

read/write bit that enables the Update End Flag (UF) bit

in Register C to assert IRQ. The SET bit going high

clears the UIE bit.

SQWE – When the Square Wave Enable (SQWE) bit is

set to a one, a square wave signal at the frequency set

by the rate–selection bits RS3 through RS0 is driven out

on a SQW pin. When the SQWE bit is set to zero, the

SQW pin is held low. SQWE is a read/write bit.

DM – The Data Mode (DM) bit indicates whether time

and calendar information is in binary or BCD format.

The DM bit is set by the program to the appropriate for-

mat and can be read as required. This bit is not modified

by internal functions. A one in DM signifies binary data

while a zero in DM specifies Binary Coded Decimal

(BCD) data.

24/12 – The 24/12 control bit establishes the format of

the hours byte. A one indicates the 24–hour mode and a

zero indicates the 12–hour mode. This bit is read/write.

DSE – The Daylight Savings Enable (DSE) bit is a read/

write bit which enables two special updates when DSE

is set to one. On the first Sunday in April the time incre-

ments from 1:59:59 AM to 3:00:00 AM. On the last

Sunday in October when the time first reaches 1:59:59

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