DS1387 datasheet(2/20 Pages) DALLAS

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DS1385/DS1387

012496 2/20

PIN DESCRIPTION

OER

– RAM Output Enable

– Crystal Input

– Crystal Output

AD0-AD7

– Mux’ed Address/Data Bus

– RTC Chip Select Input

ALE

– RTC Address Strobe

– RTC Write Data Strobe

– RTC Read Data Strobe

WER

– RAM Write Data Strobe

IRQ

– Interrupt Request Output (open

drain)

AS1

– RAM Upper Address Strobe

AS0

– RAM Lower Address Strobe

SQW

– Square Wave Output

VCC

– +5V Supply

GND

– Ground

VBAT

– Battery + Supply

BGND

– Battery Ground

– No Connection

DESCRIPTION

The DS1385/DS1387 RAMified Real Time Clocks

(RTCs) are upward–compatible successors to the in-

dustry standard DS1285/DS1287 RTC’s for PC applica-

tions. In addition to the basic DS1285/DS1287 RTC

functions, 4K bytes of on–chip nonvolatile RAM have

been added.

The RTC functions include a time–of–day clock, a one-

hundred year calendar, time–of–day interrupt, periodic

interrupts, and an end–of–clock update cycle interrupt.

In addition, 50–bytes of user NV RAM are provided with-

in this basic RTC function which can be used to store

configuration data. The clock and user RAM are main-

tained in the absence of system VCC by a lithium battery.

The 4K x 8 additional NV RAM is provided to store a

much larger amount of system configuration data than is

possible within the original 50–byte area. This RAM is

accessed via control signals separate from the RTC,

and is also maintained as nonvolatile storage from the

lithium battery.

OPERATION

The block diagram in Figure 1 shows the pin connec-

tions

with

the

major

internal

functions

the

DS1385/DS1387. The following paragraphs describe

the function of each pin.

SIGNAL DESCRIPTIONS

GND, VCC – DC power is provided to the device on

these pins. VCC is the +5 volt input. When 5 volts are

applied within normal limits, the device is fully accessi-

ble and data can be written and read. When VCC is be-

low 4.25 volts typical, reads and writes are inhibited.

However, the timekeeping function continues unaf-

fected by the lower input voltage. As VCC falls below 3

volts typical, the RAM and timekeeper are switched

over to the energy source connected to the VBAT pin in

the case of the DS1385, or to the internal battery in the

case of the DS1387. The timekeeping function main-

tains an accuracy of

±1 minute per month at 25°C re-

gardless of the voltage input on the VCC pin.

SQW (Square Wave Output) – The SQW pin can output

a signal from one of 13 taps provided by the 15 internal

divider stages of the real time clock. The frequency of the

SQW pin can be changed by programming Register A as

shown in Table 2. The SQW signal can be turned on and

off using the SQWE bit in Register B. The SQW signal is

not available when VCC is less than 4.25 volts typical.

AD0–AD7 (Multiplexed Bi–directional Address/Data

Bus) – Multiplexed buses save pins because address

information and data information time share the same

signal paths. The addresses are present during the first

portion of the bus cycle and the same pins and signal

paths are used for data in the second portion of the

cycle. Address/data multiplexing does not slow the ac-

cess time of the DS1385/DS1387 since the bus change

from address to data occurs during the internal RAM ac-

cess time. Addresses must be valid prior to the latter

portion of ALE, AS0, or AS1, at which time the

DS1385/DS1387 latches the address from AD0 to AD7.

Valid write data must be present and held stable during

the latter portion of the WR or WER pulses. In a read

cycle, the DS1385/DS1387 outputs eight bits of data

during the latter portion of the RD or OER pulses. The

read cycle is terminated and the bus returns to a high im-

pedance state as RD or OER transitions high.

ALE (RTC Address Strobe Input) – A positive going

address strobe pulse serves to demultiplex the bus.

The falling edge of ALE causes the RTC address to be

latched within the DS1385/DS1387.

RD (RTC Read Input) – RD identifies the time period

when the DS1385/DS1387 drives the bus with RTC

read data. The RD signal is an enable signal for the out-

put buffers of the clock.

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