ADS-933

®

®

6

THERMAL REQUIREMENTS

All DATEL sampling A/D converters are fully characterized

and specified over operating temperature (case) ranges of 0

+25°C) production testing is performed without the use of heat

sinks or forced-air cooling. Thermal impedance figures for

each device are listed in their respective specification tables.

These devices do not normally require heat sinks, however,

standard precautionary design and layout procedures should

be used to ensure devices do not overheat. The ground and

power planes beneath the package, as well as all pcb signal

runs to and from the device, should be as heavy as possible

to help conduct heat away from the package. Electrically

insulating, thermally-conductive "pads" may be installed

underneath the package. Devices should be soldered to

boards rather than "socketed", and of course, minimal air flow

over the surface can greatly help reduce the package

temperature.

In more severe ambient conditions, the package/junction

temperature of a given device can be reduced dramatically

(typically 35%) by using one of DATEL's HS Series heat sinks.

See Ordering Information for the assigned part number. See

page 1-183 of the DATEL Data Acquisition Components

Catalog for more information on the HS Series. Request

DATEL Application Note AN-8, "Heat Sinks for DIP Data

Converters," or contact DATEL directly, for additional

information.

Figure 3. ADS-933 Timing Diagram

This device has three pipeline delays. Four start convert pulses (clock cycles) must be applied for valid data

from the first conversion to appear at the output of the A/D.

START

CONVERT

INTERNAL S/H

N

N+1

EOC

53ns typ.

OUTPUT

DATA

Data N-4 Valid

Data N-1 Valid

Invalid

Data

Data N-2 Valid

20ns typ.

Data N Valid

265ns typ.

68ns typ.

Notes:

N+5

Conversion Time

The start convert positive pulse width must be between either 20 and 60nsec or 200 and 310nsec

(when sampling at 3MHz) to ensure proper operation. For sampling rates lower than 3MHz, the start pulse

can be wider than 310nsec, however a minimum pulse width low of 20nsec should be maintained. A 3MHz

clock with a 50nsec positive pulse width is used for all production testing.

Scale is approximately 50ns per division. fs = 3MHz.

1.

2.

3.

N+2

N+3

N+4

161ns typ.

Data N-3 Valid

178ns typ.

Acquisition Time

170ns typ.

50ns typ.

20ns typ.

Hold