EM6605

© EM Microelectonic-Marin SA, 02/99, Rev. B/243

21

10.Supply Voltage Level Detector (SVLD)

The EM6605 has a software configurable built-in supply voltage level detector. Three levels can be defined

between VDDmin + 100mV and VDDmax - 1000mV in steps of 100mV. During SLEEP mode this function is

disabled.

The required voltage compare level is selected by writing the bits VLC1 and VLC2 in the SVLD control register

which also activates the compare measurement. Since the measurement is not immediate the busy flag remains

high during the measurement and is automatically cleared low when the measurement is finished. The result is

indicated by inspection of the VLDR flag. If the result is 0 then the voltage level is higher than the selected compare

level. And if 1 is lower than the compare level.

The result VLDR of the last measurement remains until the new one is started. The start of a new measurement

resets the VLDR (SVLD result bit) to 0.

During

the

SVLD

operation

power

consumption

increases by approximately 3

$ GXULQJ RQH SHULRG RI

ck[9] (~3.9msec with *f1). The measurement internally

starts with the rising ck[9] edge following the SVLD test

command. The additional SVLD consumption stops after

the falling edge of the ck[9] internal clock.

Table 33 lists the possible voltage levels

Table 33.SVLD level selection

Evaluation voltage

VLC1

VLC0

not active

0

0

VL1 (low level)

0

1

VL2

1

0

VL3 (high level)

1

1

10.1.SVLD register

Table 34.SVLD control register - SVLD

Bit

Name

Reset

R/W

Description

3

VLDR

0

R

SVLD result (0=higher 1=lower)

2

busy

0

R

measurement in progress

1

VLC1

0

R/W

SVLD level control 1

0

VLC0

0

R/W

SVLD level control 0