EM6605 datasheet(11/43 Pages) NSC

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EM6605

Debounced PA0 is connected to CPU TestVar1

Debounced PA1 is connected to CPU TestVar2

Debounced PA2 is connected to CPU TestVar3

Figure 6.Port A

Additionally, PA3 can also be used as the input terminal for the event counter (see section 8).

The input port PA(0:3) also has individually selectable interrupts. Each port has its own interrupt mask bit in

the MPortA register. When an interrupt occurs inspection of the IRQpA and the IntRq registers allows the

source of the interrupt to be identified. The IRQpA register is automatically cleared by a RESET, by reading

the register. Reading IRQpA register also clears the INTPA flag in IntRq register. At initial RESET the

MPortA is set to 0, thus disabling any input interrupts.

See also section 9 for further details about the interrupt controller.

6.2.PortA registers

Table 12.PortA input status register - PortA

Bit

Name

Reset

R/W

Description

PA3

PA3 input status

PA2

PA2 input status

PA1

PA1 input status

PA0

PA0 input status

Table 13.PortA Interrupt request register - IRQpA

Bit

Name

Reset

R/W

Description

IRQpa3

input PA3 interrupt request flag

IRQpa2

input PA2 interrupt request flag

IRQpa1

input PA1 interrupt request flag

IRQpa0

input PA0 interrupt request flag

Table 14.PortA interrupt mask register - MportA

Bit

Name

Reset

R/W

Description

MPA3

R/W

interrupt mask for input PA3

MPA2

R/W

interrupt mask for input PA2

MPA1

R/W

interrupt mask for input PA1

MPA0

R/W

interrupt mask for input PA0

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