AD9277 datasheet(39/49 Pages) AD

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AD9277

Rev. 0 | Page 38 of 48

Table 13. Flexible Output Test Modes

Output Test Mode

Bit Sequence

Pattern Name

Digital Output Word 1

Digital Output Word 2

Subject to Data

Format Select

0000

Off (default)

N/A

0001

Midscale short

10 0000 0000 0000

Same

Yes

0010

+Full-scale short

11 1111 1111 1111

Same

Yes

0011

−Full-scale short

00 0000 0000 0000

Same

Yes

0100

Checkerboard

10 1010 1010 1010

01 0101 0101 0101

0101

PN sequence long

N/A

Yes

0110

PN sequence short

N/A

Yes

0111

One-/zero-word toggle

11 1111 1111 1111

00 0000 0000 0000

1000

User input

1001

1-/0-bit toggle

10 1010 1010 1010

N/A

1010

1× sync

00 0000 0011 1111

N/A

1011

One bit high

10 0000 0000 0000

N/A

1100

Mixed bit frequency

10 1010 0011 0011

N/A

The PN sequence long pattern produces a pseudorandom bit

sequence that repeats itself every 223 − 1 bits, or 8,388,607 bits.

A description of the PN sequence long and how it is generated

can be found in Section 5.6 of the ITU-T O.150 (05/96) standard.

The only differences are that the starting value is a specific value

instead of all 1s and that the AD9277 inverts the bit stream with

relation to the ITU-T standard (see Table 14 for the initial values).

Table 14. PN Sequence

Sequence

Initial

Value

First Three Output Samples

(MSB First)

PN Sequence Short

0x0DF

0x37E4, 0x3533, 0x0063

PN Sequence Long

0x29B80A

0x191F, 0x35C2, 0x2359

See the Memory Map section for information on how to change

these additional digital output timing features through the SPI.

SDIO Pin

This pin is required to operate the SPI. It has an internal 30 kΩ

pull-down resistor that pulls this pin low and is only 1.8 V

tolerant. If applications require that this pin be driven from a

3.3 V logic level, insert a 1 kΩ resistor in series with this pin to

limit the current.

SCLK Pin

This pin is required to operate the SPI port interface. It has an

internal 30 kΩ pull-down resistor that pulls this pin low and is

both 1.8 V and 3.3 V tolerant.

CSB Pin

This pin is required to operate the SPI port interface. It has an

internal 70 kΩ pull-up resistor that pulls this pin high and is

both 1.8 V and 3.3 V tolerant.

RBIAS Pin

To set the internal core bias current of the ADC, place a resistor

nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using a

resistor other than the recommended 10.0 kΩ resistor for RBIAS

degrades the performance of the device. Therefore, it is imperative

that at least a 1% tolerance on this resistor be used to achieve

consistent performance.

Voltage Reference

A stable and accurate 0.5 V voltage reference is built into the

AD9277. This is gained up internally by a factor of 2, setting

VREF to 1.0 V, which results in a full-scale differential input span

of 2.0 V p-p for the ADC. VREF is set internally by default, but

the VREF pin can be driven externally with a 1.0 V reference to

achieve more accuracy. However, the AD9277 does not support

ADC full-scale ranges below 2.0 V p-p.

When applying the decoupling capacitors to the VREF pin,

use ceramic, low ESR capacitors. These capacitors should be

close to the reference pin and on the same layer of the PCB as

the AD9277. The VREF pin should have both a 0.1 μF capacitor

and a 1 μF capacitor connected in parallel to the analog ground.

These capacitor values are recommended for the ADC to

properly settle and acquire the next valid sample.

The reference settings can be selected using the SPI. The settings

allow two options: using the internal reference or using an

external reference. The internal reference option is the default

setting and has a resulting differential span of 2 V p-p.

Table 15. SPI-Selectable Reference Settings

SPI-Selected Mode

Resulting

VREF (V)

Resulting Differential

Span (V p-p)

External Reference

N/A

2 × external reference

Internal Reference (Default)

1.0

2.0

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