AD9670BBCZ datasheet(33/53 Pages) AD

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AD9670

Data Sheet

Rev. A | Page 32 of 52

Table 15. Flexible Output Test Modes

Output Test Mode

Bit Sequence

Pattern Name

Digital Output Word 1

Digital Output Word 2

Subject to

Resolution Select

0000

Off (default)

Not applicable

0001

Midscale short

10 0000 0000 0000

Same

Yes

0010

+Full-scale short

11 1111 1111 1111

Same

Yes

0011

−Full-scale short

00 0000 0000 0000

Same

Yes

0100

Checkerboard

10 1010 1010 1010

01 0101 0101 0101

0101

PN sequence long

Not applicable

Yes

0110

PN sequence short

Not applicable

Yes

0111

One-/zero-word toggle

11 1111 1111 1111

00 0000 0000 0000

1000

User input

There are nine digital output test pattern options available that

can be initiated through the SPI. The test pattern options are

useful when validating receiver capture and timing. See Table 15

for the available output bit sequencing options. Some test patterns

have two serial sequential words and can be alternated in various

ways, depending on the test pattern chosen. Note that some

patterns may not adhere to the data format select option. In

addition, custom user defined test patterns can be assigned in

the user pattern registers (Address 0x019 through Address 0x01C).

All test mode options except pseudorandom number (PN)

sequence short and PN sequence long can support 8- to

14-bit word lengths to verify data capture to the receiver.

The PN sequence short pattern produces a pseudorandom

bit sequence that repeats itself every 29 − 1 bits, or 511 bits. A

description of the PN sequence short and how it is generated

can be found in Section 5.1 of the ITU-T O.150 (05/96) standard.

The only difference from the standard is that the starting value is a

specific value instead of all 1s (see Table 16 for the initial values).

The PN sequence long pattern produces a pseudorandom bit

sequence that repeats itself every 223 − 1 bits, or 8,388,607 bits.

A description of the PN sequence long and how it generates is

found in Section 5.6 of the ITU-T O.150 (05/96) standard. The

only differences from the standard are that the starting value is

a specific value instead of all 1s, and that the AD9670 inverts the

bit stream (see Table 16 for the initial values). The output sample

size depends on the selected bit length.

Table 16. PN Sequence

PN Sequence

Initial Value

First Three Output Samples

(MSB First, 16-Bit)

Short

0x092

0x496F, 0xC9A9, 0x980C

Long

0x003

0xFF5C, 0x0029, 0xB80A

See the Memory Map section for information on how to change

these additional digital output timing features via the SPI.

SDIO Pin

The SDIO pin is required to operate the SPI. It has an internal

30 kΩ pull-down resistor that pulls this pin low and is only 1.79 V

tolerant. If applications require that SDIO be driven from a

3.3 V logic level, insert a 1 kΩ resistor in series with this pin

to limit the current.

SCLK Pin

The SCLK pin is required to operate the SPI port interface. It

has an internal 30 kΩ pull-down resistor that pulls this pin low

and is only 1.8 V tolerant. To drive the SCLK pin from a 3.3 V

logic level, insert a 1 kΩ resistor in series with this pin to limit

the current.

CSB Pin

The CSB pin is required to operate the SPI port interface. CSB

has an internal 70 kΩ pull-up resistor that pulls this pin high

and is only 1.8 V tolerant. To drive the CSB pin from a 3.3 V

logic level, insert a 1 kΩ resistor in series with this pin to limit

the current.

RBIAS Pin

To set the internal core bias current of the ADC, place a resistor

nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using a

resistor other than the recommended 10.0 kΩ resistor for RBIAS

degrades the performance of the device. Therefore, it is imperative

that at least a 1% tolerance on this resistor be used to achieve

consistent performance.

VREF Pin

A stable and accurate 0.5 V voltage reference is built in to the

AD9670. This reference is gained up internally by a factor of 2,

setting VREF to 1.0 V, which results in a full-scale differential

input span of 2.0 V p-p for the ADC. VREF is set internally by

default, but the VREF pin can be driven externally with a 1.0 V

reference to achieve more accuracy. However, the AD9670 does

not support ADC full-scale ranges below 2.0 V p-p.

When applying the decoupling capacitors to the VREF pin,

use ceramic, low ESR capacitors. Place these capacitors close to

the reference pin and on the same layer of the PCB as the AD9670.

It is recommended that the VREF pin have both a 0.1 μF

capacitor and a 1 μF capacitor that are connected in parallel to

the analog ground. These capacitor values are recommended for

the ADC to properly settle and acquire the next valid sample.

General-Purpose Output Pins

The general-purpose output pins, GPO0, GPO1, GPO2, and

GPO3, can be used in a system to provide programmable inputs

to other chips in the system. The value of each pin is set via SPI

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