AD9670BBCZ datasheet(8/53 Pages) AD

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Data Sheet

AD9670

Rev. A | Page 7 of 52

DIGITAL SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C), unless

otherwise noted.

Table 2.

Parameter1

Temperature

Min

Typ

Max

Unit

INPUTS

CLK+, CLK−, TX_TRIG+, TX_TRIG−

Logic Compliance

CMOS/LVDS/LVPECL

Differential Input Voltage42

0.2

3.6

V p-p

Input Voltage Range

GND − 0.2

AVDD1 + 0.2

Input Common-Mode Voltage

0.9

Input Resistance (Differential)

25°C

kΩ

Input Capacitance

25°C

MLO+, MLO−, RESET+, RESET−

Logic Compliance

LVDS/LVPECL

Differential Input Voltage2

0.250

2 × AVDD2

V p-p

Input Voltage Range

GND − 0.2

AVDD2 + 0.2

Input Common-Mode Voltage

−0.3

AVDD2/2

+0.3

Input Resistance (Single-Ended)

25°C

kΩ

Input Capacitance

25°C

1.5

LOGIC INPUTS

PDWN, STBY, SCLK, SDIO, ADDRx

Logic 1 Voltage

1.2

DRVDD + 0.3

Logic 0 Voltage

0.3

Input Resistance3

25°C

30 (26 for SDIO)

kΩ

Input Capacitance3

25°C

2 (5 for SDIO)

CSB

Logic 1 Voltage

1.2

DRVDD + 0.3

Logic 0 Voltage

0.3

Input Resistance

25°C

kΩ

Input Capacitance

25°C

LOGIC OUTPUTS

SDIO4

Logic 1 Voltage (IOH = 800 μA)

1.79

Logic 0 Voltage (IOL = 50 μA)

0.05

GPO0/GPO1/GPO2/GPO3

Logic 0 Voltage (IOL = 50 μA)

0.05

DIGITAL OUTPUTS (DOUTx+, DOUTx−)

ANSI-644

Logic Compliance

LVDS

Differential Output Voltage (VOD)

247

454

Output Offset Voltage (VOS)

1.125

1.375

Output Coding (Default)

Offset binary

Low Power, Reduced Signal Option

Logic Compliance

LVDS

Differential Output Voltage (VOD)

150

250

Output Offset Voltage (VOS)

1.10

1.30

Output Coding (Default)

Offset binary

1 For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and

Evaluation.

2 Specified for LVDS and LVPECL only.

3 The typical input resistance and input capacitance values deviate for SDIO; these deviations are noted in the Typ column.

4 Specified for 13 SDIO pins sharing the same connection.

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