AD9670BBCZ datasheet(44/53 Pages) AD

44 / 53 page

Data Sheet

AD9670

Rev. A | Page 43 of 52

Table 27. Memory Map Registers

Addr.

(Hex)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

Comments

Chip Configuration Registers

0x000

CHIP_PORT_CONFIG

LSB first

0 = off

(default)

1 = on

SPI reset

0 = off

(default)

1 = on

SPI reset

0 = off

(default)

1 = on

LSB first

0 = off

(default)

1 = on

0x18

Mirror nibbles so

that LSB or MSB

first mode is set

correctly, regard-

less of shift mode.

An SPI reset reverts

all registers (includ-

ing the LVDS

registers), except

their default

values, and

Bits[2:5] are

automatically

cleared.

0x001

CHIP_ID

Chip ID, Bits[7:0]

(AD9670 = 0xA6) (default)

0x7C

Default is unique

chip ID, different

for each device;

read-only register.

0x002

CHIP_GRADE

Speed mode, Bits[5:4]

(identify device

variants of chip ID)

00: Mode I (40 MSPS)

(default)

01: Mode II (65 MSPS)

10: Mode III (80 MSPS)

11: Mode III (125 MSPS)

0x0X

Speed mode is used

to differentiate the

ADC speed power

modes (the user

must update

Reg. 0x0FF to

initiate the mode

setting).

0x0FF

DEVICE_UPDATE

0x00

A write to Reg.

0x0FF (the write

value does not

matter) resets all

default register

values (analog and

ADC registers only,

not LVDS registers

and not Reg. 0x000

or Reg. 0x002,

Bits[5:4]) if

been previously

written since the

last reset/load of

defaults.

0x004

DEVICE_INDEX_2

Data

Channel H

0 = off

1 = on

(default)

Data

Channel G

0 = off

1 = on

(default)

Data

Channel F

0 = off

1 = on

(default)

Data

Channel E

0 = off

1 = on

(default)

0x0F

Bits are set to

determine which

on-chip device

receives the next

write command.

0x005

DEVICE_INDEX_1

Clock

channel

DCO±

0 = off

1 = on

(default)

Clock

channel

FCO±

0 = off

1 = on

(default)

Data

Channel D

0 = off

1 = on

(default)

Data

Channel C

0 = off

1 = on

(default)

Data

Channel B

0 = off

1 = on

(default)

Data

Channel A

0 = off

1 = on

(default)

0x3F

Bits are set to

determine which

on-chip device

receives the next

write command.

0x008

GLOBAL_MODES

LNA input

imped-

ance

0 = 6 kΩ

(default)

1 = 3 kΩ

Internal power-down mode

000 = chip run (TGC mode)

001 = full power-down (default)

010 = standby

011 = reset all LVDS registers

100 = CW mode (TGC power-down)

0x01

Determines the

generic modes of

chip operation

(global).

0x009

GLOBAL_CLOCK

DCS

0 = off

1 = on

(default)

0x01

Turns the internal

DCS on and off

(global).

0x00A

PLL_STATUS

PLL lock

status

0 = not

locked

1 = locked

0x00

Monitors the PLL

lock status (read

only, global).

AD9670BBCZ Datasheet(PDF) 44 Page - Analog Devices

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