AD9670BBCZ datasheet(38/53 Pages) AD

38 / 53 page

Data Sheet

AD9670

Rev. A | Page 37 of 52

High-Pass Filter

A second-order Butterworth, high-pass infinite impulse response

(IIR) filter can be applied after the RF decimator. The filter has a

settling time of 2.5 μs and a cutoff of 700 kHz for an encode

clock of 50 MHz. Therefore, if the ADC clock is 50 MHz, the

first 125 samples (2.5 μs/0.02 μs) must be ignored. The filter

can be bypassed or enabled in the vector profile if the filter is

enabled in Register 0x113, Bit 5. If the filter is bypassed by

setting Register 0x113, Bits[5:1], the filter cannot be enabled

from the vector profile.

BASEBAND DEMODULATOR AND DECIMATOR

The demodulator downconverts the RF signal to a baseband

quadrature signal. The decimator reduces the excess oversampling.

Numerically Controlled Oscillator

The numerically controlled oscillator (NCO) generates I and Q

signals (cos and −sin) for the demodulator. A division of the

effective sample clock generates the oscillator frequency. If the

RF decimator is bypassed, the effective sample clock is the same

as the ADC clock. If the RF decimator is enabled, the effective

clock rate is ½ the ADC sample clock frequency. The divider is

set in the vector profile. The oscillator has a frequency resolution

of 1 kHz. To synchronize different devices, the NCO is reset

upon assertion of the TX_TRIG signal.

Decimation Filter

The purpose of the decimation filter is to band limit the

demodulated signal prior to decimation. The filter is a

polyphase FIR filter that uses 16 taps per decimation with

symmetrical coefficients. Therefore, there are eight unique,

14-bit coefficients per decimation. The decimation rate and a

pointer to the coefficients used by the filter are set in the vector

profile. Digital gain from 1 to 128 is applied to the filter response.

The digital gain compensation is set in the vector profile.

The filter is reset upon assertion of the TX_TRIG signal. The

decimation filter takes 32× the decimation input samples or

32 output samples to populate.

Coefficient Memory

The coefficient memory stores the eight coefficients per

decimation, with a maximum decimation of 32, in a coefficient

memory block. At a maximum decimation of 32, 32 × 8 = 256

coefficients are needed. The coefficient memory is available at

Address 0x1000 to Address 0x1FFF. This is sufficient space to

store up to 2048 coefficients. Each vector profile has a pointer, P, to

the coefficient block within coefficient memory.

Coefficients are written using the SPI in stream mode during

startup. Coefficients are written in 14-bit × 8-word = 112-bit

blocks. There are 256 coefficient blocks. The 14-bit × 8-word

coefficients are packed into 14 bytes × 8 bits, as shown in Table 22.

Table 22. Coefficient Memory for M = 4

j\i

Writes and reads from a coefficient block must begin on a

coefficient block boundary, and an entire coefficient block must

be written or read. After a coefficient block is written, the

coefficient block address automatically increments/decrements

(depending on the LSB/MSB SPI setting in Register 0x000) to

the next coefficient block.

Having a direct map between the SPI memory address and

coefficient block address requires a divide by 7, which is not

simple to do in hardware (the address must be mapped within a

single cycle). Therefore, each block is padded to a 16-byte

boundary, but the SPI does not need to shift in these extra

2 bytes when loading coefficient memory sequentially. If the

SPI is configured LSB first, the SPI address bits, Bits[3:0], are all

0s. If the SPI is configured MSB first, the SPI address bits are all

1s. In other words, in LSB mode, the referenced addresses for

the coefficient memory blocks are 0x1000, 0x2000, and so on,

while in MSB SPI mode, the referenced block addresses are

0x100F, 0x200F, and so on.

The coefficient block order and how words/bytes are split across

each other are shown in Table 23. When the SPI is configured

LSB first, C0[0] = B0[0] is written first, and C7[13] = B13[7] is

written last. When the SPI is configured MSB first, C7[13] =

B13[7] is written first, and C0[0] = B0[0] is written last.

The position of a coefficient, Cn, in memory is determined

from its index (i, j) by

n = M(1 + i) − (1 + j), if i is even

(8)

n = M × i + j, if i is odd

(9)

where:

M is the decimation factor.

i is the index within the coefficient block from 0 to 7.

j is the decimation phase from 0 to M − 1.

Due to symmetry, Coefficient C0 is multiplied by the newest

and oldest samples.

As an example, the coefficient memory for a decimation factor

of M = 4 is shown in Table 22.

The upper 16 bits of the filter output are used as the data output

of the channel. The filter output may have gain applied according

to g, from the vector profile. Additionally, a gain of 4× can be

applied using the filter output gain in Register 0x113, Bit 4.

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