AD9671KBCZ datasheet(33/61 Pages) AD

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AD9671

Data Sheet

Rev. A| Page 32 of 60

Link Setup Parameters

The following steps demonstrate how to configure the AD9671

JESD204B interface and the outputs.

Disable lanes before changing the configuration.

Select the converter and lane configuration.

Configure the tail bits and control bits.

Set the lane identification values.

Set the number of frame per multiframe, K.

Enable scramble, SCR.

Set the lane synchronization options.

Verify FCHK, checksum of JESD204B interface parameters.

Set additional digital output configuration options.

10. Reenable lane(s) after configuration.

Disable Lanes

Before modifying the JESD204B link parameters, disable the

link and hold it in reset. This is accomplished by writing a

Logic 1 to Address 0x142, Bit 0.

Converter and Lane Configuration

If the digital demodulator/decimator is disabled, the JESD204B

M parameter (number of converters) is set to 8 (Address 0x153 =

0x07). Otherwise M = 16 when the channel output is complex data.

The lane configuration is set in Address 0x150, Bits[1:0] such

that 00 = one lane per link, 01 = two lanes per link, or 11 = four

lanes per link. The channel data (A to H) is placed on the

JESD204B lanes according Table 16.

Table 16. Channel to JESD204B Lane Mapping

SERDOUT1±

SERDOUT2±

SERDOUT3±

SERDOUT4±

A, B, C, D, E, F,

G, H

Power-down

A, B, C, D

Power-down

E, F, G, H

Power-down

A, B

C, D

E, F

G, H

Configure the Tail Bits and Control Bits

With N’ = 16 and N = 14, two tail bits are available per sample

for transmitting additional information over the JESD204B link.

Tail bits are dummy bits sent over the link to complete the two

octets and do not convey any information about the input signal.

Tail bits can be fixed zeros (default) or pseudorandom numbers

(Address 0x142, Bit 6).

Set Lane Identification Values

JESD204B allows parameters to identify the device and lane.

These parameters are transmitted during the ILAS phase, and they

are accessible in the internal registers.

There are three identification values: device identification

(DID), bank identification (BID), and lane identification (LID).

DID and BID are device specific; therefore, they can be used for

link identification.

Table 17. JESD204B Configurable Identification Values

DID Value

Value Range

LID (SERDOUT1±)

0x148, [4:0]

0 to 31

LID (SERDOUT2±)

0x149, [4:0]

0 to 31

LID (SERDOUT3±)

0x14A, [4:0]

0 to 31

LID (SERDOUT4±)

0x14B, [4:0]

0 to 31

DID

0x146, [7:0]

0 to 255

BID

0x147, [3:0]

0 to 15

Set Number of Frames per Multiframe, K

Per the JESD204B specification, a multiframe is defined as a group

of K successive frames, where K is between 1 and 32, and it

requires that the number of octets be between 17 and 1024. The

K value is set to 32 by default in Register 0x152, Bits[4:0]. Note

that Register 0x152 represents a value of K − 1.

The K value can be changed; however, it must comply with a

few conditions. The AD9671 uses a fixed value for octets per

frame, F. K must also be a multiple of 4 and conform to the

following equation:

32 ≥ K ≥ Ceil (17/F)

The JESD204B specification also requires that the number of

octets per multiframe (K × F) be between 17 and 1024. The F

value is fixed based on the value of M and L. F can be read from

Address 0x151.





Enable Scramble, SCR

Scrambling can be enabled or disabled by setting Address 0x150,

Bit 7. By default, scrambling is enabled. Per the JESD204B protocol,

scrambling is only functional after the lane synchronization is

complete.

Set Lane Synchronization Options

Most of the synchronization features of the JESD204B interface

are enabled by default for typical applications. In some cases,

these features can be disabled or modified as follows.

ILAS enabling is controlled in Address 0x142, Bits[3:2] and is

enabled by default. Optionally, to support some unique instances of

the interfaces (such as NMCDA-SL), the JESD204B interface

can be programmed to either disable the ILAS sequence or

continually repeat the ILAS sequence. Additionally, the ILAS can

be repeated for a fixed count, as programmed in Address 0x145,

Bits[7:0].

The AD9671 has fixed values of some of the JESD204B interface

parameters, and they are as follows:



N’ = 16: number of bits per sample is 16. Read only value

from Address 0x155, Bits[3:0] = 15 (N’ − 1).



CF = 0: number of control words per frame clock cycle per

converter is 0, in Address 0x157, Bits[4:0].

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