SL28610

...................... DOC #: SP-AP-0078 (Rev. 1.0) Page 14 of 23

CPU_STP# Assertion

The CPU_STP# signal is an active LOW input used for

synchronous stopping and starting the CPU output clocks

while the rest of the clock generator continues to function.

When the CPU_STP# pin is asserted, all CPU outputs that are

set with the SMBus configuration to be stoppable are stopped

within two to six CPU clock periods after sampled by two rising

edges of the internal CPUC clock. The final states of the

stopped CPU signals are CPUT = HIGH and CPUC = LOW.

CPU_STP# Deassertion

The deassertion of the CPU_STP# signal causes all stopped

CPU outputs to resume normal operation in a synchronous

manner. No short or stretched clock pulses are produced when

the

clock

resumes.

The

maximum

latency

from

the

deassertion to active outputs is no more than two CPU clock

cycles.

.

.

Note: *Differential clocks output state can be configured through Byte 19 bits 3:.0

CPU_STP#

CPUT

CPUC

Figure 4. CPU_STP# Assertion Waveform

CPU_STP#

CPUT

CPUC

CPUT Internal

Tdrive_CPU_STP#,10 ns>200 mV

CPUC Internal

Figure 5. CPU_STP# Deassertion Waveform

Table 1. Output Driver Status during PCI_STPPCI_STP# and CPU_STP#

CPU_STP# Asserted

SMBus Disabled

OE# Pins Disabled

Single-ended Clocks

Stoppable

Running

Driven low

Driven low

Non stoppable

Running

Differential Clocks

Stoppable

Clock driven high

Driven Low

Clock driven high*

Clock# driven low

Clock# driven low*

Non stoppable

Running