SL28610 datasheet(2/23 Pages) SILABS

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SL28610

........................ DOC #: SP-AP-0078 (Rev. 1.0) Page 2 of 23

Pin Definitions

Pin No.

Name

Type

Description

CPU_STP#

I, SE

3.3V input for CPU_STP# (active low) functionality

CKPWRGD#/PD

I, SE

3.3V LVTTL input (active low)

XOUT

O, SE 3.3V, 14.31818MHz crystal output (When used a clock input, float XOUT)

XIN/CLKIN

I, SE

3.3V, 14.31818MHz crystal input, 3.3V Clock Input.

VDD3.3V

PWR

3.3V power supply for single-ended clock

REF / PCIe_SEL

IO, PD,

3.3V, 14.31818MHz output / 1.5V input active high signal latched on CKPWRGD#

signal to select PCIe from PLL3 (share with LCD PLL; 100K-ohm internal pull-down)

VSS

GND

Ground

VDD1.5_CORE

PWR

1.5V power supply for core

FSC

I, SE

1.05V Frequency Select C

TEST_MODE

I, SE

3.3V-tolerant input to selects Ref/N or Tri-state when in test mode.

0 = Tri-state, 1 = Ref/N

TEST_SEL

I, SE

3.3V-tolerant input to selects TEST_SEL

0 = Normal, 1 = Test Entry

SCLK

I, SE

3.3V SMBus Clock Line

SDATA

I/O, SE 3.3V SMBus Data Line

VDD1.5_CORE

PWR

1.5V power supply for core

VDD1.5_IO

PWR

1.5V power supply for differential outputs

DOT96#

O, DIFF Fixed complimentary 96MHz clock output

DOT96

O, DIFF Fixed true 96MHz clock output

VSS

GND

Ground

VSS

GND

Ground

LCD_SSC#

O, DIF Complementary 100MHz Differential clock

LCD_SSC

O, DIF True 100MHz Differential clock

VDD1.5_IO

PWR

1.5V power supply for differential outputs

VDD1.5_CORE

PWR

1.5V power supply for core

OE_0#

I, SE

Output enable for PCIe0, (10K-ohm internal pull-up)

0 =enable, 1=disable

VSS

GND

Ground

PCIe0#

O, DIF Complementary 100MHz Differential clock

PCIe0

O, DIF True 100MHz Differential clock

OE_1#

I, SE

Output enable for PCIe1, (10K-ohm internal pull-up)

0 =enable, 1=disable

VDD1.5_CORE

PWR

1.5V Power Supply for core

VDD1.5_IO

PWR

1.5V Power Supply for differential output

PCIe1#

O, DIF Complementary 100MHz Differential clock

PCIe1

O, DIF True 100MHz Differential clock

VSS

GND

Ground

PCIe2#

O, DIF Complementary 100MHz Differential clock

PCIe2

O, DIF True 100MHz Differential clock

OE_2#

I, SE

Output enable for PCIe2, (10K-ohm internal pull-up)

0 =enable, 1=disable

FSB

I, SE

1.05V Frequency Select B

CPU0#

O, DIF Complementary Host Differential clock

CPU0

O, DIF True Host Differential clock

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