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LT3471

3471f

OPERATIO

The LT3471 uses a constant frequency, current mode

control scheme to provide excellent line and load regula-

tion. Refer to the Block Diagram. At the start of each

oscillator cycle, the SR latch is set, which turns on the

power switch, Q1 (Q2). A voltage proportional to the

switch current is added to a stabilizing ramp and the

resulting sum is fed into the positive terminal of the PWM

comparator A2 (A4). When this voltage exceeds the level

at the negative input of A2 (A4), the SR latch is reset,

turning off the power switch Q1 (Q2). The level at the

negative input of A2 (A4) is set by the error amplifier A1

(A3) and is simply an amplified version of the difference

between the negative feedback voltage and the positive

feedback voltage, usually tied to the reference voltage

VREG. In this manner, the error amplifier sets the correct

peak current level to keep the output in regulation. If the

error amplifier’s output increases, more current is deliv-

ered to the output. Similarly, if the error decreases, less

current is delivered. Each switcher functions indepen-

dently but they share the same oscillator and thus the

switchers are always in phase. Enabling the part is done by

taking either SHDN/SS pin above 1.8V. Disabling the part

is done by grounding both SHDN/SS pins. The soft-start

feature of the LT3471 allows for clean start-up conditions

by limiting the amount of voltage rise at the output of

comparator A1 and A2, which in turn limits the peak

switching current. The soft-start feature for each switcher

is enabled by slowly ramping that switcher’s SHDN/SS pin,

using an RC network, for example. Typical resistor and

capacitor values are 0.33µF and 4.7kΩ, allowing for a

start-up time on the order of milliseconds. The LT3471 has

a current limit circuit not shown in the Block Diagram. The

switch current is constantly monitored and not allowed to

exceed the maximum switch current (typically 1.6A). If the

switch current reaches this value, the SR latch is reset

regardless of the state of the comparator A2 (A4). Also not

shown in the Block Diagram is the thermal shutdown

circuit. If the temperature of the part exceeds approxi-

mately 160°C, both latches are reset regardless of the state

of comparators A2 and A4. The current limit and thermal

shutdown circuits protect the power switch as well as the

external components connected to the LT3471.

APPLICATIONS INFORMATION

Duty Cycle

The typical maximum duty cycle of the LT3471 is 94%.

The duty cycle for a given application is given by:

OUT

CESAT

|| |

| – |

|| |

| – |

Where VD is the diode forward voltage drop and VCESAT is

in the worst case 330mV (at 1.3A)

The LT3471 can be used at higher duty cycles, but it must

be operated in the discontinuous conduction mode so that

the actual duty cycle is reduced.

Setting Output Voltage

Setting the output voltage depends on the topology used.

For normal noninverting boost regulator topologies:

OUT

FBP

⎛

⎝

⎜

⎞

⎠

⎟

where VFBN is connected between R1 and R2 (see the

Typical Applications section for examples).

Select values of R1 and R2 according to the following

equation:

OUT

REF

⎛

⎝

⎜

⎞

⎠

⎟

–

A good value for R2 is 15k which sets the current in the

resistor divider chain to 1.00V/15k = 67µA.

VFBP is usually just tied to VREF = 1.00V, but VFBP can also

be tied to a divided down version of VREF or some other

voltage as long as the absolute maximum ratings for the

feedback pins are not exceeded (see Absolute Maximum

Ratings).

For inverting topologies, VFBN is tied to ground and VFBP

is connected between R1 and R2. R2 is between VFBP and

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