AD8370 datasheet(17/28 Pages) AD

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AD8370

Rev. 0 | Page 17 of 28

Due to the nature of the AD8370’s circuit design, care must be

taken to minimize parasitic capacitance on the input and output.

The AD8370 could become unstable with more than a few pF of

shunt capacitance on each input. Using resistors in series with

input pins is recommended under conditions of high source

capacitance.

High transient and noise levels on the power supply, ground,

and digital inputs can, under some circumstances, reprogram the

AD8370 to an unintended gain code. This further reinforces the

need for proper supply bypassing and decoupling. The user

should also be aware that probing the AD8370 and associated

circuitry during circuit debug may also induce the same effect.

PACKAGE CONSIDERATIONS

The package of the AD8370 is a compact, thermally enhanced

TSSOP 16-lead design. A large exposed paddle on the bottom of

the device provides both a thermal benefit and a low inductance

path to ground for the circuit. To make proper use of this pack-

aging feature, the PCB needs to make contact directly under the

device, connected to an ac/dc common ground reference with

as many vias as possible to lower the inductance and thermal

impedance.

SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION

AD8370

SERIAL CONTROL

INTERFACE

0.1

µF

1nF

0.1

µF

+VS

CAC

SINGLE-

ENDED

SOURCE

Figure 45. Single-Ended-to-Differential Conversion

The AD8370 is primarily designed for differential signal inter-

facing. The device can be used for single-ended-to-differential

conversion simply by terminating the unused input to ground

using a capacitor as depicted in Figure 45. The ac coupling

capacitors should be selected such that their reactance is negli-

gible at the frequency of operation. For example, using 1 nF

capacitors for CAC presents a capacitive reactance of –j1.6 Ω on

each input node at 100 MHz. This attenuates the applied input

voltage by 0.003 dB. If 10 pF capacitors had been selected, the

voltage delivered to the input would be reduced by 2.1 dB when

operating with a 200 Ω source impedance.

–1.0

–0.5

0.5

100

200

300

400

500

FREQUENCY (MHz)

HIGH GAIN MODE

(GAIN CODE HG255)

LOW GAIN MODE

(GAIN CODE LG127)

Figure 46. Differential Output Balance for a Single-Ended Input Drive at

Maximum Gain (RL = 1 kΩ, CAC = 10 nF)

Figure 46 illustrates the differential balance at the output for a

single-ended input drive for multiple gain codes. The differential

balance is better than 0.5 dB for signal frequencies less than

250 MHz. Figure 47 depicts the differential balance over the

entire gain range at 10 MHz. The balance is degraded for lower

gain settings because the finite common gain allows some of the

input signal applied to INHI to pass directly through to the

OPLO pin. At higher gain settings, the differential gain dominates

and balance is restored.

0.1

0.2

0.3

0.4

0.5

0.6

326496

128

GAIN CODE

LOW GAIN MODE

HIGH GAIN MODE

Figure 47. Differential Output Balance at 10 MHz for a Single-Ended Drive vs.

Gain Code (RL = 1 kΩ, CAC = 10 nF)

Even though the amplifier is no longer being driven in a bal-

anced manner, the distortion performance remains adequate for

most applications. Figure 48 illustrates the harmonic distortion

performance of the circuit in Figure 45 over the entire gain range.

If the amplifier is driven in single-ended mode, the input

impedance varies depending on the value of the resistor used to

terminate the other input as follows:

RinSE = RinDIFF + RTERM

where RTERM is the termination resistor connected to the other

input.

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