S29CD032J datasheet(21/74 Pages) CYPRESS

21 / 74 page

Document Number: 002-00948 Rev. *C

Page 21 of 74

S29CD032J

S29CD016J

S29CL032J

S29CL016J

7.3

Hardware Reset (RESET#)

The RESET# pin is an active low signal that is used to reset the device under any circumstances. A logic “0” on this input forces the

device out of any mode that is currently executing back to the reset state. RESET# may be tied to the system reset circuitry. A

system reset would thus also reset the device. To avoid a potential bus contention during a system reset, the device is isolated from

the DQ data bus by tristating the data outputs for the duration of the RESET pulse. All data outputs are “don’t care” during the reset

operation.

If RESET# is asserted during a program or erase operation, the RY/BY# output remains low until the reset operation is internally

complete. The RY/BY# pin can be used to determine when the reset operation is complete. Since the device offers simultaneous

read/write operation, the host system may read a bank after a period of tREADY2, if the bank was in the read/reset mode at the time

RESET# was asserted. If one of the banks was in the middle of either a program or erase operation when RESET# was asserted,

the user must wait a period of tREADY before accessing that bank.

Asserting RESET# during a program or erase operation leaves erroneous data stored in the address locations being operated on at

the time of device reset. These locations need updating after the reset operation is complete. See Hardware Reset (RESET#)

on page 56 for timing specifications.

Asserting RESET# active during VCC and VIO power-up is required to guarantee proper device initialization until VCC and VIO have

reached their steady state voltages. See VCC and VIO Power-up on page 52.

7.4

Synchronous (Burst) Read Mode and Configuration Register

When a series of adjacent addresses need to be read from the device, the synchronous (or burst read) mode can be used to

significantly reduce the overall time needed for the device to output array data. After an initial access time required for the data from

the first address location, subsequent data is output synchronized to a clock input provided by the system.

The device offers a linear method of burst read operation which is discussed in 2-, 4-, 8- Double Word Linear Burst Operation

on page 22.

Since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration register must be set in

order to enable the burst read mode. Other Configuration Register settings include the number of wait states to insert before the

initial word (tIACC) of each burst access and when RDY indicates that data is ready to be read. Prior to entering the burst mode, the

system first determines the configuration register settings (and read the current register settings if desired via the Read

Configuration Register command sequence), then write the configuration register command sequence. See Configuration Register

on page 24, and Table 34 on page 67 for further details. Once the configuration register is written to enable burst mode operation,

all subsequent reads from the array are returned using the burst mode protocols.

Figure 2. Synchronous/Asynchronous State Diagram

Power-up/

Hardware Reset

Asynchronous Read

Mode Only

Synchronous Read

Mode Only

Set Burst Mode

Configuration Register

Command for

Synchronous Mode

(D15 = 0)

Set Burst Mode

Configuration Register

Command for

Asynchronous Mode

(D15 = 1)

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