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S29CD032J Datasheet(PDF) 28 Page - Cypress Semiconductor |
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S29CD032J Datasheet(HTML) 28 Page - Cypress Semiconductor |
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28 / 74 page ![]() Document Number: 002-00948 Rev. *C Page 28 of 74 S29CD032J S29CD016J S29CL032J S29CL016J Figure 5. Program Operation Note 38.See Table 30 and Table 35 for program command sequence. 7.7.2 Sector Erase The sector erase function erases one or more sectors in the memory array. (See Table 34. Memory Array Command Definitions (x32 Mode) on page 67 and Figure 6 Erase Operation on page 29.) The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all-zero data pattern prior to electrical erase. After a successful sector erase, all locations within the erased sector contain FFFFh. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than 80 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 80 µs. Any sector erase address and command following the exceeded time-out (80 µs) may or may not be accepted. A time-out of 80 µs from the rising edge of the last WE# (or CE#) initiates the execution of the Sector Erase command(s). If another falling edge of the WE# (or CE#) occurs within the 80 µs time-out window, the timer is reset. Any command other than Erase Suspend during the time-out period will be interpreted as an additional sector to erase. The device does not decode the data bus, but latches the address. (See S29CD016J Sector Erase Time-Out Functionality Application Note for further information.). The system can monitor DQ3 to determine if the sector erase timer has timed out (See DQ3: Sector Erase Timer on page 35.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data; addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to Write Operation Status on page 32 for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be re-initiated once that bank has returned to reading array data, in order to ensure data integrity. Figure 6 on page 29 illustrates the algorithm for the erase operation. Refer to Program/Erase Operations on page 27 for parameters and timing diagrams. START Write Program Command Sequence Data Poll from System Verify Data? No Yes Last Address? No Yes Programming Completed Increment Address Embedded Program algorithm in progress |
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