6

TMP1075

SBOS854 – MARCH 2018

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6.6 Timing Requirements

see the Timing Diagrams and Two-Wire Timing Diagrams sections for additional information

FAST MODE

HIGH-SPEED

MODE

UNIT

MIN

MAX

MIN

MAX

SCL operating frequency

V+

0.001

0.4

0.001

2.38

MHz

Bus-free time between STOP and START

conditions

See the Timing

Diagrams section

1300

160

ns

Hold time after repeated START condition.

After this period, the first clock is generated.

600

160

ns

Repeated START condition setup time

600

160

ns

600

160

ns

4

900

4

120

ns

100

10

ns

SCL clock low period

V+, see the Timing

Diagrams section

1300

280

ns

SCL clock high period

See the Timing

Diagrams section

600

60

ns

Data fall time

See the Timing

Diagrams section

300

150

ns

Clock rise time

See the Two-Wire

Timing Diagrams section

300

40

ns

SCLK

≤ 100 kHz, see

the Timing Diagrams

section

1000

Clock fall time

See the Two-Wire

Timing Diagrams section

300

40

ns

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

SCL= 12.5 MHz

50

ns