Frame 1 Two Wire Slave Address

Byte

Frame 2 Pointer Register Byte

Frame 4 Data Byte 2

1

Start By

Master

ACK By

Device

ACK By

Device

ACK By

Device

Stop By

Master

1

D7

D6

D5

D4

D3

D2

D 1

D0

9

Frame 3 Data Byte 1

ACK By

Device

1

D7

SDA

(Continued)

SCL

(Continued)

D6

D5

D 4

D3

D2

D1

D0

9

9

SDA

SCL

0

0

1

A2

A1

A 0

R/W

0

0

0

0

0

0

P1

P0

«

«

1

9

1

SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(BUF)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

P

S

S

P

11

TMP1075

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7.3.3 Timing Diagrams

various operations on the TMP1075. The following list provides bus definitions. Parameters for Figure 1 are

defined in the Timing Requirements.

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line, from high to low when the SCL line is high defines a

START condition. Each data transfer is initiated with a START condition.

Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a

STOP condition. Each data transfer is terminated with a repeated START or STOP condition.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and

is determined by the master device. The receiver acknowledges the transfer of data.

Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device

that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA

line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into

account. On a master receive, the termination of the data transfer can be signaled by the master generating a

Not-Acknowledge on the last byte that is transmitted by the slave.

7.3.4 Two-Wire Timing Diagrams

Figure 1. Two-Wire Timing Diagram

Figure 2. Two-Wire Timing Diagram for the TMP1075 Write Word Format