23

LTC4212

4212f

Table 6. N-Channel Selection Guide

CURRENT LEVEL (A)

PART NUMBER

DESCRIPTION

MANUFACTURER

0 to 2

MMDF3N02HD

Dual N-Channel SO-8

ON Semiconductor

2 to 5

MMSF5N02HD

Single N-Channel SO-8

ON Semiconductor

5 to 10

MTB50N06V

Single N-Channel DD Pak

ON Semiconductor

10 to 20

MTB75N05HD

Single N-Channel DD Pak

ON Semiconductor

Table 7. Manufacturers’ Web Sites

MANUFACTURER

WEB SITE

TEMIC Semiconductor

www.temic.com

International Rectifier

www.irf.com

ON Semiconductor

www.onsemi.com

Harris Semiconductor

www.semi.harris.com

IRC-TT

www.irctt.com

Vishay-Dale

www.vishay.com

Vishay-Siliconix

www.vishay.com

Diodes, Inc.

www.diodes.com

APPE DIX

PACKAGE DESCRIPTIO

MS Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661)

MSOP (MS) 0603

0.53

± 0.152

(.021

± .006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 – 0.27

(.007 – .011)

TYP

0.127

± 0.076

(.005

± .003)

0.86

(.034)

REF

0.50

(.0197)

BSC

12 3 45

4.90

± 0.152

(.193

± .006)

0.497

± 0.076

(.0196

± .003)

REF

8

9

10

7 6

3.00

± 0.102

(.118

± .004)

(NOTE 3)

3.00

± 0.102

(.118

± .004)

(NOTE 4)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010)

0

° – 6° TYP

DETAIL “A”

DETAIL “A”

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889

± 0.127

(.035

± .005)

RECOMMENDED SOLDER PAD LAYOUT

0.305

± 0.038

(.0120

± .0015)

TYP

0.50

(.0197)

BSC

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.