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ISL6744ABZ Datasheet(PDF) 12 Page - Intersil Corporation |
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ISL6744ABZ Datasheet(HTML) 12 Page - Intersil Corporation |
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12 / 18 page ![]() 12 FN9147.8 September 22, 2005 The RMS current through each primary side FET can be determined from EQ. 10, substituting 5A of primary current for IOUT (assuming 100% duty cycle). The result is 3.5A RMS. Fairchild FDS3672 FETs, rated at 100V and 7.5A (rDS(ON) = 22mΩ), were selected for the half-bridge switches. The synchronous rectifier FETs must withstand approximately one half of the input voltage assuming no switching transients are present. This suggests that a device capable of withstanding at least 30V is required. Empirical testing in the circuit revealed switching transients of 20V were present across the device indicating a rating of at least 60V is required. The RMS current rating of 7.07A for each SR FET requires a low rDS(ON) to minimize conduction losses, which is difficult to find in a 60V device. It was decided to use two devices in parallel to simplify the thermal design. Two Fairchild FDS5670 devices are used in parallel for a total of four SR FETs. The FDS5670 is rated at 60V and 10A (rDS(ON) = 14mΩ). Oscillator Component Selection The desired operating frequency of 235kHz for the converter was established in the Design Criteria section. The oscillator frequency operates at twice the frequency of the converter because two clock cycles are required for a complete converter period. During each oscillator cycle the timing capacitor, CT, must be charged and discharged. Determining the required discharge time to achieve zero voltage switching (ZVS) is the critical design goal in selecting the timing components. The discharge time sets the deadtime between the two outputs, and is the same as ZVS transition time. Once the discharge time is determined, the remainder of the period becomes the charge time. The ZVS transition duration is determined by the transformer’s primary leakage inductance, Llk, by the FET Coss, by the transformer’s parasitic winding capacitance, and by any other parasitic elements on the node. The parameters may be determined by measurement, calculation, estimate, or by some combination of these methods. Device output capacitance, Coss, is non-linear with applied voltage. To find the equivalent discrete capacitance, Cfet, a charge model is used. Using a known current source, the time required to charge the MOSFET drain to the desired operating voltage is determined and the equivalent capacitance is calculated. Once the estimated transition time is determined, it must be verified directly in the application. The transformer leakage inductance was measured at 125nH and the combined capacitance was estimated at 2000pF. Calculations indicate a transition period of ~25ns. Verification of the performance yielded a value of TD closer to 45ns. The remainder of the switching half-period is the charge time, TC, and can be found from where FSw is the converter switching frequency. Using Figure 3, the capacitor value appropriate to the desired oscillator operating frequency of 470kHz can be selected. A CT value of 100pF, 150pF, or 220pF is appropriate for this frequency. A value of 150pF was selected. To obtain the proper value for RTD, EQ. 3 is used. Since there is a 10ns propagation delay in the oscillator circuit, it must be included in the calculation. The value of RTD selected is 10k Ω. Output Filter Design The output filter inductor and capacitor selection is simple and straightforward. Under steady state operating conditions the voltage across the inductor is very small due to the large duty cycle. Voltage is applied across the inductor only during the switch transition time, about 45ns in this application. Ignoring the voltage drop across the SR FETs, the voltage across the inductor during the on time with VIN = 48V is where VL is the inductor voltage VS is the voltage across the secondary winding VOUT is the output voltage If we allow a current ramp, ∆I, of 5% of the rated output current, the minimum inductance required is An inductor value of 1.5 µH, rated for 18A was selected. With a maximum input voltage of 53V, the maximum output voltage is about 13V. The closest higher voltage rated capacitor is 16V. Under steady state operating conditions the ripple current in the capacitor is small, so it would seem appropriate to have a low ripple current rated capacitor. However, a high rated ripple current capacitor was selected tzvs π L lk 2Coss Cxfrmr + () • 2 -------------------------------------------------------------------- ≈ s (EQ. 12) Cfet Ichg t • V -------------------- = F (EQ. 13) TC 1 2FSw • -------------------- TD – 1 2 235 10 3 • • ---------------------------------- 45 10 9 – • – 2.08 == = µs (EQ. 14) VL VS VOUT – VIN NS 1D – () • • 2NP ------------------------------------------------ 250 ≈ == mV (EQ. 15) L VL TON • ∆I ------------------------- ≥ 0.25 2.08 • 0.5 ----------------------------- 1.04 == µH (EQ. 16) ISL6744 |
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