ISL6744ABZ datasheet(14/18 Pages) INTERSIL

14 / 18 page

FN9147.8

September 22, 2005

Waveforms

Typical waveforms can be found in the following Figures.

Figure 13 shows the output voltage ripple and noise at a 5A.

Figures 14 and 15 show the voltage waveforms at the

switching node shared by the upper FET source and the

lower FET drain. In particular, Figure 15 shows near ZVS

operation at 5A of load when the upper FET is turning off

and the lower FET is turning on. ZVS operation occurs

completely, implying that all the energy stored in the node

capacitance has been recovered. Figure 16 shows the

switching transition between outputs, OUTA and OUTB

during steady state operation. The deadtime duration of

46.9ns is clearly shown.

A 2.7V zener is added between the Vdd pins of ISL6700 and

ISL6744, in order to ensure that the PWM turns on only after

the driver has turned on, thereby ensuring the soft-start

function. Figure 17 shows the soft-start operation.

FIGURE 12. LINE REGULATION AT IOUT = 1A

13.5

12.5

11.5

10.5

INPUT VOLTAGE (V)

FIGURE 13. OUTPUT RIPPLE AND NOISE - 20MHz BW

FIGURE 14. FET DRAIN-SOURCE VOLTAGE

FIGURE 15. FET D-S VOLTAGE NEAR-ZVS TRANSITION

FIGURE 16. OUTA - OUTB TRANSITION

ISL6744

ISL6744ABZ Datasheet(PDF) 14 Page - Intersil Corporation